1/*
2 * Copyright (c) 2018 - 2020 Antmicro <www.antmicro.com>
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7/ {
8	#address-cells = <1>;
9	#size-cells = <1>;
10	compatible = "litex,vexriscv", "litex-dev";
11	model = "litex,vexriscv";
12
13
14	chosen {
15		zephyr,entropy = &prbs0;
16	};
17
18	cpus {
19		#address-cells = <1>;
20		#size-cells = <0>;
21		cpu@0 {
22			clock-frequency = <100000000>;
23			compatible = "riscv";
24			device_type = "cpu";
25			reg = <0>;
26			riscv,isa = "rv32ima_zicsr_zifencei";
27			status = "okay";
28			timebase-frequency = <32768>;
29		};
30	};
31	soc {
32		#address-cells = <1>;
33		#size-cells = <1>;
34		compatible = "litex,vexriscv";
35		ranges;
36		intc0: interrupt-controller@bc0 {
37			compatible = "vexriscv-intc0";
38			#address-cells = <0>;
39			#interrupt-cells = <2>;
40			interrupt-controller;
41			reg = <0xbc0 0x4 0xfc0 0x4>;
42			reg-names = "irq_mask", "irq_pending";
43			riscv,max-priority = <7>;
44		};
45		uart0: serial@e0001800 {
46			compatible = "litex,uart0";
47			interrupt-parent = <&intc0>;
48			interrupts = <2 10>;
49			reg = <0xe0001800 0x4
50				0xe0001804 0x4
51				0xe0001808 0x4
52				0xe000180c 0x4
53				0xe0001810 0x4
54				0xe0001814 0x4
55				0xe0001818 0x4
56				0xe000181c 0x4>;
57			reg-names =
58				"rxtx",
59				"txfull",
60				"rxempty",
61				"ev_status",
62				"ev_pending",
63				"ev_enable",
64				"txempty",
65				"rxfull";
66			status = "disabled";
67		};
68		spi0: spi@e0002000 {
69			compatible = "litex,spi";
70			reg = <0xe0002000 0x4
71				0xe0002004 0x4
72				0xe0002008 0x4
73				0xe000200c 0x4
74				0xe0002010 0x4
75				0xe0002014 0x4>;
76			reg-names = "control",
77				"status",
78				"mosi",
79				"miso",
80				"cs",
81				"loopback";
82			status = "disabled";
83			#address-cells = <1>;
84			#size-cells = <0>;
85		};
86		timer0: timer@e0002800 {
87			compatible = "litex,timer0";
88			interrupt-parent = <&intc0>;
89			interrupts = <1 0>;
90			reg = <0xe0002800 0x4
91				0xe0002804 0x4
92				0xe0002808 0x4
93				0xe000280c 0x4
94				0xe0002810 0x4
95				0xe0002814 0x4
96				0xe0002818 0x4
97				0xe000281c 0x4
98				0xe0002820 0x4
99				0xe0002824 0x8>;
100			reg-names =
101				"load",
102				"reload",
103				"en",
104				"update_value",
105				"value",
106				"ev_status",
107				"ev_pending",
108				"ev_enable",
109				"uptime_latch",
110				"uptime_cycles";
111			status = "disabled";
112		};
113		eth0: ethernet@e0009800 {
114			compatible = "litex,eth0";
115			interrupt-parent = <&intc0>;
116			interrupts = <3 0>;
117			reg = <0xe0009800 0x4
118				0xe0009804 0x4
119				0xe0009808 0x4
120				0xe000980c 0x4
121				0xe0009810 0x4
122				0xe0009814 0x4
123				0xe0009818 0x4
124				0xe000981c 0x4
125				0xe0009820 0x4
126				0xe0009824 0x4
127				0xe0009828 0x4
128				0xe000982c 0x4
129				0xe0009830 0x4
130				0xe0009834 0x4
131				0xb0000000 0x2000>;
132			local-mac-address = [10 e2 d5 00 00 02];
133			reg-names = "rx_slot",
134				"rx_length",
135				"rx_errors",
136				"rx_ev_status",
137				"rx_ev_pending",
138				"rx_ev_enable",
139				"tx_start",
140				"tx_ready",
141				"tx_level",
142				"tx_slot",
143				"tx_length",
144				"tx_ev_status",
145				"tx_ev_pending",
146				"tx_ev_enable",
147				"buffers";
148			status = "disabled";
149		};
150		dna0: dna@e0003800 {
151			compatible = "litex,dna0";
152			/* DNA data is 57-bits long,
153			so it requires 8 bytes.
154			In LiteX each 32-bit register holds
155			only a single byte of meaningful data,
156			hence 8 registers. */
157			reg = <0xe0003800 0x20>;
158			reg-names = "mem";
159			status = "disabled";
160		};
161		i2c0: i2c@e0005000 {
162			compatible = "litex,i2c";
163			reg = <0xe0005000 0x4 0xe0005004 0x4>;
164			reg-names = "write", "read";
165			#address-cells = <1>;
166			#size-cells = <0>;
167			status = "disabled";
168		};
169		gpio_out: gpio@e0005800 {
170			compatible = "litex,gpio";
171			reg = <0xe0005800 0x4>;
172			reg-names = "control";
173			ngpios = <4>;
174			port-is-output;
175			status = "disabled";
176			gpio-controller;
177			#gpio-cells = <2>;
178		};
179		gpio_in: gpio@e0006000 {
180			compatible = "litex,gpio";
181			reg = <0xe0006000 0x4
182				0xe0006004 0x4
183				0xe0006008 0x4
184				0xe0006010 0x4
185				0xe0006014 0x4>;
186			interrupt-parent = <&intc0>;
187			interrupts = <4 2>;
188			reg-names = "base",
189				"irq_mode",
190				"irq_edge",
191				"irq_pend",
192				"irq_en";
193			ngpios = <4>;
194			status = "disabled";
195			gpio-controller;
196			#gpio-cells = <2>;
197		};
198		prbs0: prbs@e0006800 {
199			compatible = "litex,prbs";
200			reg = <0xe0006800 0x4>;
201			reg-names = "status";
202			status = "disabled";
203		};
204		pwm0: pwm@e0007000 {
205			compatible = "litex,pwm";
206			reg = <0xe0007000 0x4 0xe0007004 0x10 0xe0007014 0x10>;
207			reg-names = "enable", "width", "period";
208			status = "disabled";
209			#pwm-cells = <2>;
210		};
211		i2s_rx: i2s_rx@e000a800 {
212			compatible = "litex,i2s";
213			reg = <0xe000a800 0x4
214				0xe000a804 0x4
215				0xe000a808 0x4
216				0xe000a80c 0x4
217				0xe000a810 0x4
218				0xe000a814 0x4
219				0xb1000000 0x40000>;
220			interrupt-parent = <&intc0>;
221			interrupts = <6 2>;
222			#address-cells = <1>;
223			#size-cells = <0>;
224			reg-names = "ev_status",
225				"ev_pending",
226				"ev_enable",
227				"rx_ctl",
228				"rx_stat",
229				"rx_conf",
230				"fifo";
231			fifo_depth = <256>;
232			status = "disabled";
233		};
234		i2s_tx: i2s_tx@e000b000 {
235			compatible = "litex,i2s";
236			reg = <0xe000b000 0x4
237				0xe000b004 0x4
238				0xe000b008 0x4
239				0xe000b00c 0x4
240				0xe000b010 0x4
241				0xe000b014 0x4
242				0xb2000000 0x40000>;
243			interrupt-parent = <&intc0>;
244			interrupts = <7 2>;
245			#address-cells = <1>;
246			#size-cells = <0>;
247			reg-names = "ev_status",
248				"ev_pending",
249				"ev_enable",
250				"tx_ctl",
251				"tx_stat",
252				"tx_conf",
253				"fifo";
254			fifo_depth = <256>;
255			status = "disabled";
256		};
257		clock-outputs {
258			#address-cells = <1>;
259			#size-cells = <0>;
260			clk0: clock-controller@0 {
261				#clock-cells = <1>;
262				reg = <0>;
263				compatible = "litex,clkout";
264				clock-output-names = "CLK_0";
265				litex,clock-frequency = <11289600>;
266				litex,clock-phase = <0>;
267				litex,clock-duty-num = <1>;
268				litex,clock-duty-den = <2>;
269				litex,clock-margin = <1>;
270				litex,clock-margin-exp = <2>;
271				status = "disabled";
272			};
273			clk1: clock-controller@1 {
274				#clock-cells = <1>;
275				reg = <1>;
276				compatible = "litex,clkout";
277				clock-output-names = "CLK_1";
278				litex,clock-frequency = <22579200>;
279				litex,clock-phase = <0>;
280				litex,clock-duty-num = <1>;
281				litex,clock-duty-den = <2>;
282				litex,clock-margin = <1>;
283				litex,clock-margin-exp = <2>;
284				status = "disabled";
285			};
286		};
287		clock0: clock@e0004800 {
288			compatible = "litex,clk";
289			reg = <0xe0004800 0x4
290				0xe0004804 0x4
291				0xe0004808 0x4
292				0xe000480c 0x4
293				0xe0004810 0x4
294				0xe0004814 0x4
295				0xe0004818 0x4
296				0xe000481c 0x4>;
297			reg-names = "drp_reset",
298				"drp_locked",
299				"drp_read",
300				"drp_write",
301				"drp_drdy",
302				"drp_adr",
303				"drp_dat_w",
304				"drp_dat_r";
305			#clock-cells = <1>;
306			clocks = <&clk0 0>, <&clk1 1>;
307			clock-output-names = "CLK_0", "CLK_1";
308			litex,lock-timeout = <10>;
309			litex,drdy-timeout = <10>;
310			litex,sys-clock-frequency = <100000000>;
311			litex,divclk-divide-min = <1>;
312			litex,divclk-divide-max = <107>;
313			litex,clkfbout-mult-min = <2>;
314			litex,clkfbout-mult-max = <65>;
315			litex,vco-freq-min = <600000000>;
316			litex,vco-freq-max = <1200000000>;
317			litex,clkout-divide-min = <1>;
318			litex,clkout-divide-max = <126>;
319			litex,vco-margin = <0>;
320			status = "disabled";
321		};
322	};
323};
324