1# Copyright (c) 2019 Nordic Semiconductor ASA 2# SPDX-License-Identifier: Apache-2.0 3 4description: | 5 QSPI NOR flash supporting the JEDEC CFI interface. 6 7compatible: "nordic,qspi-nor" 8 9include: [base.yaml, "jedec,spi-nor-common.yaml"] 10 11on-bus: qspi 12 13properties: 14 reg: 15 required: true 16 17 jedec-id: 18 required: true 19 20 size: 21 type: int 22 description: | 23 The size in bits. Set this or size-in-bytes, but not both. 24 25 size-in-bytes: 26 type: int 27 description: | 28 The size in bytes. Set this or size, but not both. 29 30 # Match original driver NORDIC_QSPI_NOR_QE_BIT Kconfig default. 31 quad-enable-requirements: 32 default: "S1B6" 33 34 readoc: 35 type: string 36 enum: 37 - "fastread" # Single data line SPI, FAST_READ (0x0B) 38 - "read2o" # Dual data line SPI, READ2O (0x3B) 39 - "read2io" # Dual data line SPI, READ2IO (0xBB) 40 - "read4o" # Quad data line SPI, READ4O (0x6B) 41 - "read4io" # Quad data line SPI, READ4IO (0xEB) 42 description: | 43 Specify the number of data lines and opcode used for reading. 44 If not provided fastread will be selected. 45 46 writeoc: 47 type: string 48 enum: 49 - "pp" # Single data line SPI, PP (0x02) 50 - "pp2o" # Dual data line SPI, PP2O (0xA2) 51 - "pp4o" # Quad data line SPI, PP4O (0x32) 52 - "pp4io" # Quad data line SPI, PP4IO (0x38) 53 description: | 54 Specify the number of data lines and opcode used for writing. 55 If not provided pp will be selected. 56 57 address-size-32: 58 type: boolean 59 description: | 60 Set to indicate that 32-bit addressing is to be used. 61 If not specified 24-bit addressing will be used. 62 63 ppsize-512: 64 type: boolean 65 description: | 66 Set to indicate that the write opcode operates on 512-byte pages. 67 If not specified the write opcode operates on 256-byte pages. 68 69 sck-delay: 70 type: int 71 default: 0 72 description: | 73 Number of clock cycles CSn must be asserted before it can go low 74 again, specified in nanoseconds. 75 76 rx-delay: 77 type: int 78 description: | 79 Number of clock cycles from the rising edge of the SPI clock 80 until the input serial data is sampled. 81 82 cpha: 83 type: boolean 84 description: | 85 Set to indicate phase starts with asserted half-phase (CPHA=1). 86 For this driver using this property requires also using cpol. 87 88 cpol: 89 type: boolean 90 description: | 91 Set to indicate clock leading edge is falling (CPOL=1). 92 For this driver using this property requires also using cpha. 93 94 sck-frequency: 95 type: int 96 required: true 97 description: | 98 Maximum clock speed supported by the device, in Hz. 99