1# Copyright 2023 NXP
2# SPDX-License-Identifier: Apache-2.0
3
4description: |
5  NXP S32 eMIOS PWM node for S32 SoCs. Each channel in eMIOS can be configured
6  to use for PWM operation. There are several PWM modes supported by this module,
7  some modes only support on channels that have internal counter, some modes
8  require to use a reference timebase from a master bus.
9
10  For example to configuring eMIOS instance 0 with:
11    - Channel 0 for mode OPWFMB
12    - Channel 1 for mode OPWMB
13    - Channel 2 for mode OPWMCB with deadtime inserted at leading edge
14    - Channel 3 for mode SAIC, use internal timebase with input filter = 2 eMIOS clock
15
16    emios0_pwm: pwm {
17      pwm_0 {
18        channel = <0>;
19        pwm-mode = "OPWFMB";
20        prescaler = <8>;
21        period = <65534>;
22        duty-cycle = <32768>;
23        polarity = "ACTIVE_HIGH";
24      };
25
26      pwm_1 {
27        channel = <1>;
28        master-bus = <&emios1_bus_a>;
29        pwm-mode = "OPWMB";
30        duty-cycle = <32768>;
31        phase-shift = <100>;
32        polarity = "ACTIVE_LOW";
33      };
34
35      pwm_2 {
36        channel = <2>;
37        master-bus = <&emios1_bus_b>;
38        pwm-mode = "OPWMCB_LEAD_EDGE";
39        duty-cycle = <32768>;
40        dead-time = <100>;
41        polarity = "ACTIVE_LOW";
42      };
43
44      pwm_3 {
45        channel = <3>;
46        pwm-mode = "SAIC";
47        prescaler = <8>;
48        input-filter = <2>;
49      };
50    };
51
52  OPWMB and OPWMCB modes use reference timebase, the master bus is chosen over
53  phandle 'master-bus'. For OPWMB mode, PWM's period is master bus's period and
54  is 2 * master bus's period - 2 for OPWMCB mode. Please notice that the devicetree
55  node for master bus should be enabled and configured for using, please see
56  'nxp,s32-emios' bindings.
57
58compatible: "nxp,s32-emios-pwm"
59
60include: [pwm-controller.yaml, base.yaml, pinctrl-device.yaml]
61
62properties:
63  pinctrl-0:
64    required: true
65
66  pinctrl-names:
67    required: true
68
69  "#pwm-cells":
70    const: 3
71
72pwm-cells:
73  - channel
74  # Period in terms of nanoseconds
75  - period
76  - flags
77
78child-binding:
79  description: |
80    eMIOS PWM channel configuration.
81
82  properties:
83    channel:
84      type: int
85      required: true
86      description: eMIOS PWM channel
87
88    master-bus:
89      type: phandle
90      description: |
91        A phandle to master-bus node that will be used as external timebase
92        for current channel, this can be bypassed if internal counter is used
93        for PWM operation. A master bus must be used exclusively, such as if
94        is used as a timebase for a channel in SAIC mode, do not use that
95        master bus as a timebase for generate PWM pulse.
96
97    pwm-mode:
98      type: string
99      required: true
100      description: |
101        Select PWM mode:
102        - OPWFMB: provides waveforms with variable duty cycle and frequency,
103                  this mode uses internal counter.
104
105        - OPWMB:  generate pulses with programmable leading and trailing
106                  edge placement. The period is determined by period of
107                  an external counter driven in MCB Up Mode. Changing PWM period
108                  at runtime will impact to all channels share the same timebase.
109                  The new period and cycle take effect in next period boundary.
110
111        - OPWMCB: generates a center aligned PWM with dead time insertion to the
112                  leading or trailing edge. The period is determined by period of
113                  an external counter driven in MCB Up Down Mode. Changing PWM period
114                  at runtime will impact to all channels share the same timebase,
115                  The new period and cycle take effect in next period boundary.
116
117        - SAIC: single action input capture mode, the eMIOS captures events as soon as
118                they occur. The value of latest captured event is stored and can be read
119                by software.
120      enum:
121        - "OPWFMB"
122        - "OPWMB"
123        - "OPWMCB_TRAIL_EDGE"
124        - "OPWMCB_LEAD_EDGE"
125        - "SAIC"
126
127    polarity:
128      type: string
129      description: |
130        Output polarity for PWM channel.
131      enum:
132        - "ACTIVE_LOW"
133        - "ACTIVE_HIGH"
134
135    duty-cycle:
136      type: int
137      description: |
138        Duty-cycle (in ticks) for PWM channel at boot time.
139
140    period:
141      type: int
142      description: |
143        Period (in ticks) for OPWFMB at boot time. Period for the rest
144        of PWM mode depends on period's master bus. Must be in range [2 ... 65535].
145
146    freeze:
147      type: boolean
148      description: Freeze individual internal counter when the chip enters Debug mode.
149
150    prescaler-src:
151      type: string
152      default: "PRESCALED_CLOCK"
153      description: |
154        Select clock source for internal counter prescaler.
155      enum:
156        - "PRESCALED_CLOCK" # Clock source = eMIOS clock / (global prescaler)
157        - "MODULE_CLOCK"    # Clock source = eMIOS clock
158
159    prescaler:
160      type: int
161      description: |
162        The clock divider for internal counter prescaler.
163      enum: [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16]
164
165    dead-time:
166      type: int
167      default: 0
168      description: |
169        Dead time (in ticks) for PWM channel in OPWMCB mode.
170
171    phase-shift:
172      type: int
173      default: 0
174      description: |
175        Phase Shift (in ticks) for PWM channel in OPWMB mode.
176
177    input-filter:
178      type: int
179      default: 0
180      enum: [0, 2, 4, 8, 16]
181      description: |
182        Select the minimim input pulse width, in filter clock cycles that can pass
183        through the input filter. The filter latency - the difference in time between
184        the input and the response is three clock edges. Default 0 means the filter
185        is bypassed. The clock source for programmable input filter is eMIOS clock.
186