1# Copyright (c) 2020 Antmicro <www.antmicro.com> 2# SPDX-License-Identifier: Apache-2.0 3 4include: base.yaml 5 6description: | 7 LiteX Mixed Mode Clock Manager clock output binding 8 9compatible: "litex,clkout" 10 11properties: 12 13 "#clock-cells": 14 required: true 15 type: int 16 description: | 17 Number of cells in a clock specifier; 18 Typically 0 for nodes with a single clock output 19 and 1 for nodes with multiple clock outputs. 20 const: 1 21 22 clock-output-names: 23 required: true 24 type: string 25 description: | 26 string of clock output signal name. 27 28 litex,clock-frequency: 29 required: true 30 type: int 31 description: | 32 default frequency in Hz for clock output 33 34 litex,clock-phase: 35 required: true 36 type: int 37 description: | 38 default phase offset given in degrees 39 40 litex,clock-duty-num: 41 required: true 42 type: int 43 description: | 44 default duty cycle numerator value 45 46 litex,clock-duty-den: 47 required: true 48 type: int 49 description: | 50 default duty cycle denominator value 51 52 litex,clock-margin: 53 required: true 54 type: int 55 description: | 56 clock output margin coefficient 57 58 litex,clock-margin-exp: 59 required: true 60 type: int 61 description: | 62 exponent for clkout margin 63 effective clkout margin shall be 64 margin * 10^(-exponent) * 100% 65 66clock-cells: 67 - id 68
