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/Zephyr-latest/tests/drivers/clock_control/stm32_clock_configuration/stm32_common_devices/src/
Dtest_stm32_clock_configuration_i2c.c4 * SPDX-License-Identifier: Apache-2.0
28 static void i2c_set_clock(const struct stm32_pclken *clk) in i2c_set_clock() argument
35 (clock_control_subsys_t) clk, in i2c_set_clock()
40 /* Test clock source */ in i2c_set_clock()
43 if (clk->bus == STM32_SRC_HSI) { in i2c_set_clock()
47 } else if (clk->bus == STM32_SRC_SYSCLK) { in i2c_set_clock()
52 zassert_true(0, "Unexpected domain clk (0x%x)", dev_actual_clk_src); in i2c_set_clock()
55 /* Test status of the used clk source */ in i2c_set_clock()
57 (clock_control_subsys_t)clk); in i2c_set_clock()
58 zassert_true((status == CLOCK_CONTROL_STATUS_ON), "I2C1 clk src must to be on"); in i2c_set_clock()
[all …]
Dtest_stm32_clock_configuration_lptim.c4 * SPDX-License-Identifier: Apache-2.0
46 TC_PRINT("LPTIM1 source clock configured\n"); in ZTEST()
48 /* Test clock source */ in ZTEST()
60 zassert_true(0, "Unexpected domain clk (%d)", dev_actual_clk_src); in ZTEST()
63 /* Test get_rate(srce clk) */ in ZTEST()
67 zassert_true((r == 0), "Could not get LPTIM1 clk srce freq"); in ZTEST()
74 TC_PRINT("LPTIM1 clock source rate: %d Hz\n", dev_dt_clk_freq); in ZTEST()
83 zassert_true((r == 0), "Could not get LPTIM1 clk freq"); in ZTEST()
90 TC_PRINT("LPTIM1 clock source rate: %d Hz\n", dev_dt_clk_freq); in ZTEST()
96 zassert_true((r == 0), "Could not disable LPTIM1 gating clk"); in ZTEST()
[all …]
Dtest_stm32_clock_configuration_i2s.c4 * SPDX-License-Identifier: Apache-2.0
44 /* Test clock source */ in ZTEST()
52 zassert_true(0, "Unexpected domain clk (0x%x)", dev_actual_clk_src); in ZTEST()
55 /* Test get_rate(srce clk) */ in ZTEST()
59 zassert_true((r == 0), "Could not get I2S clk srce freq"); in ZTEST()
63 "Expected freq: %d Hz. Actual clk: %d Hz", in ZTEST()
66 TC_PRINT("I2S2 clock source rate: %d Hz\n", dev_dt_clk_freq); in ZTEST()
68 /* Test clock_off(gating clk) */ in ZTEST()
71 zassert_true((r == 0), "Could not disable I2S gating clk"); in ZTEST()
73 zassert_true(!__HAL_RCC_SPI2_IS_CLK_ENABLED(), "I2S2 gating clk should be off"); in ZTEST()
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Dtest_stm32_clock_configuration_adc.c4 * SPDX-License-Identifier: Apache-2.0
33 #define PERIPHCLK_ADC (-1)
35 #define GET_ADC_SOURCE() (-1);
46 #define ADC_SOURCE_PLL (-1)
54 #define ADC_SOURCE_SYSCLK (-1)
90 TC_PRINT("ADC1 source clock configured\n"); in ZTEST()
92 /* Test clock source */ in ZTEST()
93 zassert_true((ADC_SOURCE_PLL != -1), "Invalid ADC_SOURCE_PLL defined for target."); in ZTEST()
112 zassert_true(0, "Unexpected src clk (%d)", dev_actual_clk_src); in ZTEST()
115 /* Test status of the used clk source */ in ZTEST()
[all …]
Dtest_stm32_clock_configuration_sdmmc.c4 * SPDX-License-Identifier: Apache-2.0
48 /* CLK 48 is enabled through the clock-mux */ in ZTEST()
57 r = -127; in ZTEST()
63 /* Test clock source */ in ZTEST()
68 "Expected SDMMC src: CLK 48 (0x%lx). Actual src: 0x%x", in ZTEST()
75 zassert_true(0, "Unexpected domain clk (0x%x)", dev_actual_clk_src); in ZTEST()
78 /* Test get_rate(srce clk) */ in ZTEST()
80 /* Get the CK48M source : PLL Q or PLLI2S Q */ in ZTEST()
107 r = -127; in ZTEST()
110 zassert_true((r == 0), "Could not get SDMMC clk srce freq"); in ZTEST()
[all …]
/Zephyr-latest/dts/bindings/watchdog/
Dnxp,wdog32.yaml2 # SPDX-License-Identifier: Apache-2.0
20 clk-source:
23 description: Watchdog counter clock source
25 clk-divider:
/Zephyr-latest/tests/drivers/clock_control/stm32_clock_configuration/stm32u5_devices/src/
Dtest_stm32_clock_configuration.c4 * SPDX-License-Identifier: Apache-2.0
53 /* Test clock_on(domain source) */ in ZTEST()
57 zassert_true((r == 0), "Could not configure SPI domain clk"); in ZTEST()
58 TC_PRINT("SPI1 domain clk configured\n"); in ZTEST()
60 /* Test clk source */ in ZTEST()
72 zassert_true(1, "Unexpected clk src (0x%x)", spi1_actual_domain_clk); in ZTEST()
75 /* Test get_rate(source clk) */ in ZTEST()
79 zassert_true((r == 0), "Could not get SPI clk freq"); in ZTEST()
83 "Expected SPI clk: %d. Actual: %d", in ZTEST()
96 "Expected SPI clk freq: %d. Actual: %d", in ZTEST()
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/Zephyr-latest/dts/bindings/adc/
Dnxp,adc12.yaml2 # SPDX-License-Identifier: Apache-2.0
8 include: [adc-controller.yaml, pinctrl-device.yaml]
17 clk-source:
20 description: converter clock source
22 clk-divider:
27 alternate-voltage-reference:
29 description: use alternate voltage reference source
31 sample-time:
36 vref-mv:
41 "#io-channel-cells":
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Dnxp,vf610-adc.yaml2 # SPDX-License-Identifier: Apache-2.0
6 compatible: "nxp,vf610-adc"
8 include: [adc-controller.yaml, "nxp,rdc-policy.yaml"]
17 clk-source:
21 Select adc clock source: 0 clock from IPG, 1 clock from IPG divided 2, 2 async clock
23 clk-divider:
30 "#io-channel-cells":
33 io-channel-cells:
34 - input
Dnxp,lpc-lpadc.yaml2 # SPDX-License-Identifier: Apache-2.0
6 compatible: "nxp,lpc-lpadc"
8 include: [adc-controller.yaml, pinctrl-device.yaml]
17 clk-divider:
21 clk-source:
23 description: source to attach the ADC clock to
25 voltage-ref:
32 - 0
33 - 1
34 - 2
[all …]
/Zephyr-latest/dts/bindings/clock/
Dst,stm32g0-hsi-clock.yaml2 # SPDX-License-Identifier: Apache-2.0
8 It also produces a HSISYS secondary clk which can be used as system clock
9 source. In that case, a HSI divisor (ranges from 1 to 128) can be applied:
12 - 1 ==> HSISYS = 16MHZ
13 - 2 ==> HSISYS = 8MHZ
14 - 4 ==> HSISYS = 4MHZ
15 - 8 ==> HSISYS = 2MHZ
16 - 16 ==> HSISYS = 1MHZ
17 - 32 ==> HSISYS = 0.5MHz
18 - 64 ==> HSISYS = 0.25MHZ
[all …]
Dnuvoton,numaker-pcc.yaml2 # SPDX-License-Identifier: Apache-2.0
6 compatible: "nuvoton,numaker-pcc"
8 include: [clock-controller.yaml, base.yaml]
11 "#clock-cells":
14 clock-cells:
15 - clock-module-index # Same as u32ModuleIdx on invoking BSP CLK driver CLK_SetModuleClock()
16 - clock-source # Same as u32ClkSrc on invoking BSP CLK driver CLK_SetModuleClock()
17 - clock-divider # Same as u32ClkDiv on invoking BSP CLK driver CLK_SetModuleClock()
Despressif,esp32-rtc.yaml2 # SPDX-License-Identifier: Apache-2.0
6 compatible: "espressif,esp32-rtc"
8 include: [clock-controller.yaml, base.yaml]
14 fast-clk-src:
18 RTC fast clock source.
19 - 0: ESP32_RTC_FAST_CLK_SRC_XTAL_D2 - Main XTAL divided by 2 (C3/S3)
21 - 1: ESP32_RTC_FAST_CLK_SRC_RC_FAST - 8 MHz
23 - 0
24 - 1
26 slow-clk-src:
[all …]
Drenesas,smartbond-lp-clock.yaml2 # SPDX-License-Identifier: Apache-2.0
6 compatible: "renesas,smartbond-lp-clk"
9 - name: base.yaml
10 property-allowlist:
11 - status
12 - compatible
15 clock-src:
18 Low power clock source.
/Zephyr-latest/dts/bindings/can/
Dnxp,flexcan.yaml2 # SPDX-License-Identifier: Apache-2.0
13 interrupt-names = "warning", "error", "wake-up", "mb-0-15";
15 clk-source = <1>;
16 pinctrl-0 = <&pinmux_flexcan0>;
17 pinctrl-names = "default";
19 can-transceiver {
20 max-bitrate = <1000000>;
26 include: ["can-controller.yaml", "pinctrl-device.yaml"]
38 clk-source:
41 description: CAN engine clock source
/Zephyr-latest/drivers/clock_control/
Dclock_control_rpi_pico.c2 * Copyright (c) 2022 Andrei-Edward Popa
5 * SPDX-License-Identifier: Apache-2.0
14 #include <zephyr/dt-bindings/clock/rpi_pico_rp2040_clock.h>
16 #include <zephyr/dt-bindings/clock/rpi_pico_rp2350_clock.h>
57 #define CLK_SRC_IS(clk, src) \ argument
58 DT_SAME_NODE(DT_CLOCKS_CTLR_BY_IDX(DT_INST_CLOCKS_CTLR_BY_NAME(0, clk), 0), \
68 * Using the 'clock-names[0]' for expanding macro to frequency value.
69 * The 'clock-names[0]' is set same as label value that given to the node itself.
70 * Use it for traverse clock tree to find root of clock source.
72 #define CLOCK_FREQ(clk) _CONCAT(CLOCK_FREQ_, clk) argument
[all …]
/Zephyr-latest/dts/bindings/timer/
Dambiq,stimer.yaml2 # SPDX-License-Identifier: Apache-2.0
17 clk-source:
21 clk-source specifies the clock source that used by the system timer.
23 0 - NOCLK : No clock enabled.
24 1 - HFRC_DIV16 : 3MHz from the HFRC clock divider.
25 2 - HFRC_DIV256 : 187.5KHz from the HFRC clock divider.
26 3 - XTAL_DIV1 : 32768Hz from the crystal oscillator.
27 4 - XTAL_DIV2 : 16384Hz from the crystal oscillator.
28 5 - XTAL_DIV32 : 1024Hz from the crystal oscillator.
29 6 - LFRC_DIV1 : Approximately 1KHz from the LFRC oscillator (uncalibrated).
[all …]
/Zephyr-latest/dts/arm/nxp/
Dnxp_mcxa156.dtsi4 * SPDX-License-Identifier: Apache-2.0
8 #include <arm/armv8-m.dtsi>
9 #include <zephyr/dt-bindings/clock/mcux_lpc_syscon_clock.h>
10 #include <zephyr/dt-bindings/gpio/gpio.h>
11 #include <zephyr/dt-bindings/i2c/i2c.h>
15 #address-cells = <1>;
16 #size-cells = <0>;
19 compatible = "arm,cortex-m33f";
21 #address-cells = <1>;
22 #size-cells = <1>;
[all …]
Dnxp_s32k1xx.dtsi2 * Copyright 2023-2024 NXP
4 * SPDX-License-Identifier: Apache-2.0
8 #include <arm/armv7-m.dtsi>
9 #include <zephyr/dt-bindings/i2c/i2c.h>
17 #address-cells = <1>;
18 #size-cells = <0>;
28 compatible = "nxp,port-pinctrl";
33 interrupt-parent = <&nvic>;
41 ftfc: flash-controller@40020000 {
42 compatible = "nxp,kinetis-ftfc";
[all …]
Dnxp_s32z27x_r52.dtsi2 * Copyright 2022-2024 NXP
4 * SPDX-License-Identifier: Apache-2.0
8 #include <arm/armv8-r.dtsi>
9 #include <zephyr/dt-bindings/interrupt-controller/arm-gic.h>
10 #include <zephyr/dt-bindings/clock/nxp_s32z2_clock.h>
11 #include <zephyr/dt-bindings/i2c/i2c.h>
15 #address-cells = <1>;
16 #size-cells = <0>;
20 compatible = "arm,cortex-r52";
26 compatible = "arm,cortex-r52";
[all …]
/Zephyr-latest/dts/bindings/counter/
Dambiq,counter.yaml2 # SPDX-License-Identifier: Apache-2.0
17 clock-frequency:
22 clk-source:
25 description: Counter clock source
Datmel,sam-tc.yaml1 # SPDX-License-Identifier: Apache-2.0
5 compatible: "atmel,sam-tc"
8 - name: base.yaml
9 - name: pinctrl-device.yaml
25 Valid range: 0 - 2
27 clk:
30 Clock source selection as defined by TCCLKS bit-field of TC_CMR
36 If set to true the `clk` property is ignored. Instead the TC module is
40 reg-cmr:
47 properties like channel-num, pinctrl-0 this allows e.g. to configure
[all …]
/Zephyr-latest/soc/nxp/mcx/mcxc/
Dsoc.c4 * SPDX-License-Identifier: Apache-2.0
28 #define CLOCK_NODEID(clk) DT_CHILD(DT_INST(0, nxp_kinetis_sim), clk) argument
30 #define CLOCK_DIVIDER(clk) DT_PROP_OR(CLOCK_NODEID(clk), clock_div, 1) - 1 argument
53 .outSrc = kMCGLITE_ClkSrcHirc, /* MCGOUTCLK source is HIRC */
56 /* Low-frequency Reference Clock Divider */
58 /* Second Low-frequency Reference Clock Divider */
60 .hircEnableInNotHircMode = true, /* HIRC source is enabled */
99 /* Set LPUART0 clock source. */ in clock_init()
104 /* All TPM instances share common clock source for counter clock. in clock_init()
105 * Select the clock source using an arbitrary enabled TPM node. in clock_init()
[all …]
/Zephyr-latest/tests/boards/espressif/rtc_clk/
DKconfig2 # SPDX-License-Identifier: Apache-2.0
4 mainmenu "RTC CLK Test Configuration"
6 source "Kconfig.zephyr"
/Zephyr-latest/drivers/memc/
Dmemc_stm32.c4 * SPDX-License-Identifier: Apache-2.0
41 const struct memc_stm32_config *config = dev->config; in memc_stm32_init()
44 const struct device *clk; in memc_stm32_init() local
47 r = pinctrl_apply_state(config->pcfg, PINCTRL_STATE_DEFAULT); in memc_stm32_init()
54 clk = DEVICE_DT_GET(STM32_CLOCK_CONTROL_NODE); in memc_stm32_init()
56 if (!device_is_ready(clk)) { in memc_stm32_init()
58 return -ENODEV; in memc_stm32_init()
61 r = clock_control_on(clk, (clock_control_subsys_t)&config->pclken[0]); in memc_stm32_init()
67 if (IS_ENABLED(STM32_FMC_DOMAIN_CLOCK_SUPPORT) && (config->pclk_len > 1)) { in memc_stm32_init()
68 /* Enable FMC clock source */ in memc_stm32_init()
[all …]

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