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/Zephyr-latest/dts/bindings/i3c/
Dnxp,mcux-i3c.yaml4 # SPDX-License-Identifier: Apache-2.0
8 compatible: "nxp,mcux-i3c"
10 include: [i3c-controller.yaml, pinctrl-device.yaml]
19 i3c-od-scl-hz:
25 clk-divider:
27 description: Main clock divider for I3C
30 clk-divider-tc:
32 description: TC clock divider for I3C
35 clk-divider-slow:
37 description: Slow clock divider for I3C
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/Zephyr-latest/drivers/clock_control/
Dclock_control_r8a779f0_cpg_mssr.c7 * SPDX-License-Identifier: Apache-2.0
16 #include <zephyr/dt-bindings/clock/renesas_cpg_mssr.h>
17 #include <zephyr/dt-bindings/clock/r8a779f0_cpg_mssr.h>
88 switch (clk_info->module) { in r8a779f0_cpg_enable_disable_core()
90 reg = sys_read32(DEVICE_MMIO_GET(dev) + clk_info->offset); in r8a779f0_cpg_enable_disable_core()
95 reg = sys_read32(DEVICE_MMIO_GET(dev) + clk_info->offset); in r8a779f0_cpg_enable_disable_core()
100 ret = -ENOTSUP; in r8a779f0_cpg_enable_disable_core()
105 rcar_cpg_write(DEVICE_MMIO_GET(dev), clk_info->offset, reg); in r8a779f0_cpg_enable_disable_core()
110 static int r8a779f0_cpg_core_clock_endisable(const struct device *dev, struct rcar_cpg_clk *clk, in r8a779f0_cpg_core_clock_endisable() argument
114 struct r8a779f0_cpg_mssr_data *data = dev->data; in r8a779f0_cpg_core_clock_endisable()
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Dclock_control_r8a7795_cpg_mssr.c6 * SPDX-License-Identifier: Apache-2.0
14 #include <zephyr/dt-bindings/clock/renesas_cpg_mssr.h>
15 #include <zephyr/dt-bindings/clock/r8a7795_cpg_mssr.h>
82 switch (clk_info->module) { in r8a7795_cpg_enable_disable_core()
87 reg = sys_read32(DEVICE_MMIO_GET(dev) + clk_info->offset); in r8a7795_cpg_enable_disable_core()
95 reg = sys_read32(DEVICE_MMIO_GET(dev) + clk_info->offset); in r8a7795_cpg_enable_disable_core()
100 reg = sys_read32(DEVICE_MMIO_GET(dev) + clk_info->offset); in r8a7795_cpg_enable_disable_core()
105 ret = -ENOTSUP; in r8a7795_cpg_enable_disable_core()
110 rcar_cpg_write(DEVICE_MMIO_GET(dev), clk_info->offset, reg); in r8a7795_cpg_enable_disable_core()
115 static int r8a7795_cpg_core_clock_endisable(const struct device *dev, struct rcar_cpg_clk *clk, in r8a7795_cpg_core_clock_endisable() argument
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Dclock_control_renesas_cpg_mssr.c2 * Copyright (c) 2020-2022 IoT.bzh
4 * SPDX-License-Identifier: Apache-2.0
9 #include <zephyr/dt-bindings/clock/renesas_cpg_mssr.h>
63 if (e->module == module) { in cmp_cpg_clk_info_table_items()
65 } else if (e->module < module) { in cmp_cpg_clk_info_table_items()
68 return -1; in cmp_cpg_clk_info_table_items()
75 struct rcar_cpg_mssr_data *data = dev->data; in rcar_cpg_find_clk_info_by_module_id()
77 struct cpg_clk_info_table *table = data->clk_info_table[domain]; in rcar_cpg_find_clk_info_by_module_id()
78 uint32_t table_size = data->clk_info_table_size[domain]; in rcar_cpg_find_clk_info_by_module_id()
84 LOG_ERR("%s: can't find clk info (domain %u module %u)", dev->name, domain, id); in rcar_cpg_find_clk_info_by_module_id()
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Dclock_control_rpi_pico.c2 * Copyright (c) 2022 Andrei-Edward Popa
5 * SPDX-License-Identifier: Apache-2.0
14 #include <zephyr/dt-bindings/clock/rpi_pico_rp2040_clock.h>
16 #include <zephyr/dt-bindings/clock/rpi_pico_rp2350_clock.h>
57 #define CLK_SRC_IS(clk, src) \ argument
58 DT_SAME_NODE(DT_CLOCKS_CTLR_BY_IDX(DT_INST_CLOCKS_CTLR_BY_NAME(0, clk), 0), \
68 * Using the 'clock-names[0]' for expanding macro to frequency value.
69 * The 'clock-names[0]' is set same as label value that given to the node itself.
72 #define CLOCK_FREQ(clk) _CONCAT(CLOCK_FREQ_, clk) argument
73 #define SRC_CLOCK(clk) DT_STRING_TOKEN_BY_IDX(DT_INST_CLOCKS_CTLR_BY_NAME(0, clk), \ argument
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/Zephyr-latest/samples/sensor/lps22hh_i3c/boards/
Dmimxrt685_evk_mimxrt685s_cm33.overlay10 i2c-scl-hz = <400000>;
11 i3c-scl-hz = <400000>;
12 i3c-od-scl-hz = <400000>;
14 clk-divider = <12>;
15 clk-divider-slow = <1>;
16 clk-divider-tc = <1>;
/Zephyr-latest/samples/sensor/lsm6dso_i2c_on_i3c/boards/
Dmimxrt685_evk_mimxrt685s_cm33.overlay10 i2c-scl-hz = <400000>;
11 i3c-scl-hz = <400000>;
12 i3c-od-scl-hz = <400000>;
14 clk-divider = <12>;
15 clk-divider-slow = <1>;
16 clk-divider-tc = <1>;
/Zephyr-latest/dts/bindings/timer/
Dnuclei,systimer.yaml2 # SPDX-License-Identifier: Apache-2.0
7 The Nuclei system timer provides RISC-V privileged mtime and mtimecmp
21 clk-divider:
24 clk-divider specifies the division ratio to the CPU frequency that
35 clock-frequency = <108000000>;
44 Setting clk-divider to 2 specifies the system timer uses the clock
48 dt-bindings/timer/nuclei-systimer.h header file.
Dambiq,stimer.yaml2 # SPDX-License-Identifier: Apache-2.0
17 clk-source:
21 clk-source specifies the clock source that used by the system timer.
23 0 - NOCLK : No clock enabled.
24 1 - HFRC_DIV16 : 3MHz from the HFRC clock divider.
25 2 - HFRC_DIV256 : 187.5KHz from the HFRC clock divider.
26 3 - XTAL_DIV1 : 32768Hz from the crystal oscillator.
27 4 - XTAL_DIV2 : 16384Hz from the crystal oscillator.
28 5 - XTAL_DIV32 : 1024Hz from the crystal oscillator.
29 6 - LFRC_DIV1 : Approximately 1KHz from the LFRC oscillator (uncalibrated).
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/Zephyr-latest/dts/bindings/watchdog/
Dnxp,wdog32.yaml2 # SPDX-License-Identifier: Apache-2.0
20 clk-source:
25 clk-divider:
27 description: Watchdog counter clock divider
Dnxp,lpc-wwdt.yaml2 # SPDX-License-Identifier: Apache-2.0
6 compatible: "nxp,lpc-wwdt"
17 clk-divider:
19 description: Watchdog clock divider
/Zephyr-latest/dts/bindings/adc/
Dnxp,vf610-adc.yaml2 # SPDX-License-Identifier: Apache-2.0
6 compatible: "nxp,vf610-adc"
8 include: [adc-controller.yaml, "nxp,rdc-policy.yaml"]
17 clk-source:
23 clk-divider:
27 Select clock divider: 0 clock divided by 1, 1 clock divided by 2, 2 clock divided by 4,
30 "#io-channel-cells":
33 io-channel-cells:
34 - input
Dnxp,adc12.yaml2 # SPDX-License-Identifier: Apache-2.0
8 include: [adc-controller.yaml, pinctrl-device.yaml]
17 clk-source:
22 clk-divider:
25 description: clock divider for the converter
27 alternate-voltage-reference:
31 sample-time:
36 vref-mv:
41 "#io-channel-cells":
44 io-channel-cells:
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Dnxp,mcux-12b1msps-sar.yaml2 # SPDX-License-Identifier: Apache-2.0
6 compatible: "nxp,mcux-12b1msps-sar"
8 include: [adc-controller.yaml, pinctrl-device.yaml]
17 clk-divider:
20 description: clock divider for the converter
22 sample-period-mode:
27 "#io-channel-cells":
30 io-channel-cells:
31 - input
Dnxp,lpc-lpadc.yaml2 # SPDX-License-Identifier: Apache-2.0
6 compatible: "nxp,lpc-lpadc"
8 include: [adc-controller.yaml, pinctrl-device.yaml]
17 clk-divider:
19 description: clock divider for the converter
21 clk-source:
25 voltage-ref:
32 - 0
33 - 1
34 - 2
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/Zephyr-latest/dts/bindings/clock/
Dnuvoton,numaker-pcc.yaml2 # SPDX-License-Identifier: Apache-2.0
6 compatible: "nuvoton,numaker-pcc"
8 include: [clock-controller.yaml, base.yaml]
11 "#clock-cells":
14 clock-cells:
15 - clock-module-index # Same as u32ModuleIdx on invoking BSP CLK driver CLK_SetModuleClock()
16 - clock-source # Same as u32ClkSrc on invoking BSP CLK driver CLK_SetModuleClock()
17 - clock-divider # Same as u32ClkDiv on invoking BSP CLK driver CLK_SetModuleClock()
Dlitex,clk.yaml2 # SPDX-License-Identifier: Apache-2.0
4 include: [clock-controller.yaml, base.yaml]
12 compatible: "litex,clk"
14 clock-cells:
15 - id
22 "#clock-cells":
26 clock-output-names:
28 type: string-array
33 litex,lock-timeout:
38 litex,drdy-timeout:
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Dst,stm32g0-hsi-clock.yaml2 # SPDX-License-Identifier: Apache-2.0
8 It also produces a HSISYS secondary clk which can be used as system clock
12 - 1 ==> HSISYS = 16MHZ
13 - 2 ==> HSISYS = 8MHZ
14 - 4 ==> HSISYS = 4MHZ
15 - 8 ==> HSISYS = 2MHZ
16 - 16 ==> HSISYS = 1MHZ
17 - 32 ==> HSISYS = 0.5MHz
18 - 64 ==> HSISYS = 0.25MHZ
19 - 128 ==> HSISYS = 0.125MHz
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/Zephyr-latest/samples/drivers/i2s/i2s_codec/boards/
Dmimxrt595_evk_mimxrt595s_cm33.overlay3 i2s-codec-rx = &i2s0;
4 i2s-codec-tx = &i2s1;
9 clk-divider = <20>;
/Zephyr-latest/drivers/watchdog/
Dwdt_wwdg_stm32.c4 * SPDX-License-Identifier: Apache-2.0
40 * additionally to the internal divider, the clock is divided by a
54 * - t_WWDG: WWDG timeout
55 * - counter: a value in [0x40, 0x7F] representing the cycles before timeout.
59 * - f_WWDG: the frequency of the WWDG clock. This can be calculated by the
63 * - f_PCLK: the clock frequency of the system
64 * - 4096: the constant internal divider
65 * - prescaler: the programmable divider with valid values of 1, 2, 4 or 8,
69 * - counter = 0x40
70 * - prescaler = 1
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/Zephyr-latest/dts/bindings/can/
Dst,stm32h7-fdcan.yaml3 compatible: "st,stm32h7-fdcan"
5 include: ["bosch,m_can-base.yaml", "pinctrl-device.yaml"]
17 interrupt-names:
20 clk-divider:
23 - 1
24 - 2
25 - 4
26 - 6
27 - 8
28 - 10
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Dst,stm32-fdcan.yaml3 compatible: "st,stm32-fdcan"
5 include: ["bosch,m_can-base.yaml", "pinctrl-device.yaml"]
14 interrupt-names:
20 clk-divider:
23 - 1
24 - 2
25 - 4
26 - 6
27 - 8
28 - 10
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/Zephyr-latest/dts/bindings/video/
Dovti,ov2640.yaml2 # SPDX-License-Identifier: Apache-2.0
9 reset-gpios:
10 type: phandle-array
13 reset. The sensor receives this as an active-low signal.
15 clock-rate-control:
25 Bit[5:0] Clock divider.
27 CLK = XVCLK /(decimal value of CLKRC[5:0] + 1)
29 include: i2c-device.yaml
/Zephyr-latest/drivers/mdio/
Dmdio_xmc4xxx.c4 * SPDX-License-Identifier: Apache-2.0
30 uint8_t divider; member
35 {.divider = 8, .reg_val = 2}, {.divider = 13, .reg_val = 3},
36 {.divider = 21, .reg_val = 0}, {.divider = 31, .reg_val = 1},
37 {.divider = 51, .reg_val = 4}, {.divider = 62, .reg_val = 5},
54 const struct mdio_xmc4xxx_dev_config *const dev_cfg = dev->config; in mdio_xmc4xxx_transfer()
55 ETH_GLOBAL_TypeDef *const regs = dev_cfg->regs; in mdio_xmc4xxx_transfer()
56 struct mdio_xmc4xxx_dev_data *const dev_data = dev->data; in mdio_xmc4xxx_transfer()
60 k_mutex_lock(&dev_data->mutex, K_FOREVER); in mdio_xmc4xxx_transfer()
62 if ((regs->GMII_ADDRESS & ETH_GMII_ADDRESS_MB_Msk) != 0) { in mdio_xmc4xxx_transfer()
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/Zephyr-latest/dts/arm/nxp/
Dnxp_rt6xx_common.dtsi4 * SPDX-License-Identifier: Apache-2.0
8 #include <arm/armv8-m.dtsi>
9 #include <zephyr/dt-bindings/adc/adc.h>
10 #include <zephyr/dt-bindings/clock/mcux_lpc_syscon_clock.h>
11 #include <zephyr/dt-bindings/gpio/gpio.h>
12 #include <zephyr/dt-bindings/i2c/i2c.h>
13 #include <zephyr/dt-bindings/memory-attr/memory-attr-arm.h>
14 #include <zephyr/dt-bindings/reset/nxp_syscon_reset_common.h>
22 #address-cells = <1>;
23 #size-cells = <0>;
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