Lines Matching +full:clk +full:- +full:divider

2 # SPDX-License-Identifier: Apache-2.0
8   It also produces a HSISYS secondary clk which can be used as system clock
12         - 1 ==> HSISYS = 16MHZ
13         - 2 ==> HSISYS = 8MHZ
14         - 4 ==> HSISYS = 4MHZ
15         - 8 ==> HSISYS = 2MHZ
16         - 16 ==> HSISYS = 1MHZ
17         - 32 ==> HSISYS = 0.5MHz
18         - 64 ==> HSISYS = 0.25MHZ
19         - 128 ==> HSISYS = 0.125MHz
21 compatible: "st,stm32g0-hsi-clock"
23 include: [fixed-clock.yaml]
26   hsi-div:
30       HSI clock divider. Configures the output HSI clock frequency (HSISYS),
31       It does not apply to HSI clk selected as peripheral source clock
32       (eg: RNG clk driven by HSI)
34       - 1
35       - 2
36       - 4
37       - 8
38       - 16
39       - 32
40       - 64
41       - 128