Home
last modified time | relevance | path

Searched +full:ce +full:- +full:break +full:- +full:config (Results 1 – 14 of 14) sorted by relevance

/Zephyr-latest/tests/drivers/mspi/flash/boards/
Dnative_sim.overlay4 * SPDX-License-Identifier: Apache-2.0
15 ce-gpios = <&gpio0 5 GPIO_ACTIVE_LOW>,
17 dqs-support;
18 software-multiperipheral;
22 compatible = "zephyr,mspi-emul-flash";
25 mspi-max-frequency = <48000000>;
26 mspi-io-mode = "MSPI_IO_MODE_QUAD";
27 mspi-data-rate = "MSPI_DATA_RATE_SINGLE";
28 mspi-hardware-ce-num = <0>;
29 read-command = <0x0B>;
[all …]
Dapollo3p_evb.overlay3 * SPDX-License-Identifier: Apache-2.0
18 compatible = "ambiq,mspi-controller";
19 pinctrl-0 = <&mspi1_default>;
20 pinctrl-1 = <&mspi1_sleep>;
21 pinctrl-2 = <&mspi1_flash>;
22 pinctrl-names = "default","sleep","flash";
25 ce-gpios = <&gpio32_63 18 GPIO_ACTIVE_LOW>;
27 cmdq-buffer-location = ".mspi_buff";
28 cmdq-buffer-size = <256>;
31 compatible = "ambiq,mspi-device", "mspi-atxp032";
[all …]
/Zephyr-latest/dts/bindings/mspi/
Dmspi-device.yaml2 # SPDX-License-Identifier: Apache-2.0
8 on-bus: mspi
14 mspi-max-frequency:
22 mspi-io-mode:
25 - "MSPI_IO_MODE_SINGLE"
26 - "MSPI_IO_MODE_DUAL"
27 - "MSPI_IO_MODE_DUAL_1_1_2"
28 - "MSPI_IO_MODE_DUAL_1_2_2"
29 - "MSPI_IO_MODE_QUAD"
30 - "MSPI_IO_MODE_QUAD_1_1_4"
[all …]
Dzephyr,mspi-emul-device.yaml2 # SPDX-License-Identifier: Apache-2.0
6 compatible: "zephyr,mspi-emul-device"
8 include: mspi-device.yaml
14 xip-config:
17 scramble-config:
20 ce-break-config:
/Zephyr-latest/samples/drivers/mspi/mspi_flash/boards/
Dapollo3p_evb.overlay4 * SPDX-License-Identifier: Apache-2.0
23 pinctrl-0 = <&mspi1_default>;
24 pinctrl-1 = <&mspi1_sleep>;
25 pinctrl-2 = <&mspi1_psram>;
26 pinctrl-3 = <&mspi1_flash>;
27 pinctrl-names = "default","sleep","psram","flash";
30 ce-gpios = <&gpio64_95 5 GPIO_ACTIVE_LOW>,
33 cmdq-buffer-location = ".mspi_buff";
34 cmdq-buffer-size = <256>;
37 compatible = "ambiq,mspi-device", "mspi-aps6404l";
[all …]
/Zephyr-latest/samples/drivers/memc/boards/
Dapollo3p_evb.overlay4 * SPDX-License-Identifier: Apache-2.0
23 pinctrl-0 = <&mspi1_default>;
24 pinctrl-1 = <&mspi1_sleep>;
25 pinctrl-2 = <&mspi1_psram>;
26 pinctrl-names = "default","sleep","psram";
29 ce-gpios = <&gpio64_95 5 GPIO_ACTIVE_LOW>,
32 cmdq-buffer-location = ".mspi_buff";
33 cmdq-buffer-size = <256>;
36 compatible = "ambiq,mspi-device", "mspi-aps6404l";
40 mspi-max-frequency = <48000000>;
[all …]
/Zephyr-latest/samples/drivers/mspi/mspi_async/boards/
Dapollo3p_evb.overlay4 * SPDX-License-Identifier: Apache-2.0
23 pinctrl-0 = <&mspi1_default>;
24 pinctrl-1 = <&mspi1_sleep>;
25 pinctrl-2 = <&mspi1_psram>;
26 pinctrl-names = "default","sleep","psram";
29 ce-gpios = <&gpio64_95 5 GPIO_ACTIVE_LOW>,
32 cmdq-buffer-location = ".mspi_buff";
33 cmdq-buffer-size = <256>;
36 compatible = "ambiq,mspi-device", "mspi-aps6404l";
40 mspi-max-frequency = <48000000>;
[all …]
/Zephyr-latest/doc/hardware/peripherals/
Dmspi.rst3 Multi-bit SPI Bus
6 The MSPI (multi-bit SPI) is provided as a generic API to accommodate
16 .. _mspi-controller-api:
21 Zephyr's MSPI controller API may be used when a multi-bit SPI controller
25 not limited to high-speed, high density flash/psram memory devices, displays
30 The relationship between the controller and device drivers is many-to-many to
38 can be used, and the initialization function, config and data provided
57 to re-initialize the hardware with new parameters during runtime.
112 The mspi controller's bindings should reference mspi-controller.yaml as one of the base.
114 .. code-block:: devicetree
[all …]
/Zephyr-latest/include/zephyr/drivers/
Dmspi.h4 * SPDX-License-Identifier: Apache-2.0
219 /** @brief device gpio ce */
220 struct gpio_dt_spec ce; member
241 /** @brief GPIO chip-select line numbers (optional) */
247 /** @brief Whether to re-initialize controller */
258 struct mspi_cfg config; member
299 /** @brief Configure the time to break up a transfer into 2 */
344 * This can be used to control a CE line via a GPIO line, instead of
345 * using the controller inner CE logic.
350 * @brief GPIO devicetree specification of CE GPIO.
[all …]
/Zephyr-latest/drivers/memc/
Dmemc_mspi_aps6404l.c4 * SPDX-License-Identifier: Apache-2.0
71 const struct memc_mspi_aps6404l_config *cfg = psram->config; in memc_mspi_aps6404l_command_write()
72 struct memc_mspi_aps6404l_data *data = psram->data; in memc_mspi_aps6404l_command_write()
76 data->packet.dir = MSPI_TX; in memc_mspi_aps6404l_command_write()
77 data->packet.cmd = cmd; in memc_mspi_aps6404l_command_write()
78 data->packet.address = addr; in memc_mspi_aps6404l_command_write()
79 data->packet.data_buf = buffer; in memc_mspi_aps6404l_command_write()
80 data->packet.num_bytes = length; in memc_mspi_aps6404l_command_write()
82 data->trans.async = false; in memc_mspi_aps6404l_command_write()
83 data->trans.xfer_mode = MSPI_PIO; in memc_mspi_aps6404l_command_write()
[all …]
/Zephyr-latest/drivers/mspi/
Dmspi_ambiq_ap3.c4 * SPDX-License-Identifier: Apache-2.0
89 break; in mspi_set_freq()
91 LOG_INST_ERR(cfg->log, "%u,Frequency not supported!", __LINE__); in mspi_set_freq()
93 break; in mspi_set_freq()
105 LOG_INST_ERR(cfg->log, "%u, incorrect data rate, only SDR is supported.", __LINE__); in mspi_set_line()
188 if (ctx->owner) { in mspi_context_ce_control()
189 if (ctx->xfer.hold_ce && in mspi_context_ce_control()
190 ctx->xfer.ce_sw_ctrl.gpio.port != NULL) { in mspi_context_ce_control()
192 gpio_pin_set_dt(&ctx->xfer.ce_sw_ctrl.gpio, 1); in mspi_context_ce_control()
193 k_busy_wait(ctx->xfer.ce_sw_ctrl.delay); in mspi_context_ce_control()
[all …]
/Zephyr-latest/drivers/serial/
Duart_xlnx_ps.c1 /* uart_xlnx_ps.c - Xilinx Zynq family serial driver */
6 * SPDX-License-Identifier: Apache-2.0
19 * - the following macro for the number of bytes between register addresses:
42 * Comp. Xilinx Zynq-7000 Technical Reference Manual (ug585), chap. B.33
65 #define XUARTPS_CR_STOPBRK 0x00000100U /**< Stop transmission of break */
66 #define XUARTPS_CR_STARTBRK 0x00000080U /**< Set break */
104 #define XUARTPS_IXR_RBRK 0x00002000U /**< Rx FIFO break detect interrupt */
176 * of the UART are modified at run-time.
200 * of the UART are being modified at run-time.
222 * registers is described in the Zynq-7000 TRM, chapter 19.2.3 'Baud Rate
[all …]
/Zephyr-latest/scripts/west_commands/completion/
Dwest-completion.bash1 # Bash auto-completion for west subcommands and flags. To initialize, run
3 # source west-completion.bash
7 __west_previous_extglob_setting=$(shopt -p extglob)
8 shopt -s extglob
12 # bash_completion - programmable completion functions for bash 3.2+
14 # Copyright © 2006-2008, Ian Macdonald <ian@caliban.org>
15 # © 2009-2010, Bash Completion Maintainers
16 # <bash-completion-devel@lists.alioth.debian.org>
33 # http://bash-completion.alioth.debian.org/
41 # if test "${words_[cword_-1]}" = -w
[all …]
/Zephyr-latest/subsys/bluetooth/controller/ll_sw/openisa/hal/RV32M1/radio/
Dradio.c2 * Copyright (c) 2016 - 2019 Nordic Semiconductor ASA
4 * Copyright 2019 - 2020 NXP
6 * SPDX-License-Identifier: Apache-2.0
43 #define RADIO_AESCCM_HDR_MASK 0xE3 /* AES-CCM: NESN, SN, MD bits masked to 0 */
44 #define RADIO_PDU_LEN_MAX (BIT(8) - 1)
46 ((bytes) * 8 >> (__builtin_ffs(bits_per_usec) - 1))
52 #define RX_WTMRK 5 /* (AA + PDU header) - 1 */
138 uint8_t bytes[CAU3_AES_BLOCK_SIZE - 1 - 2];
139 } nonce; /* used by the B0 format but not in-situ */
157 uint32_t tmr = GENFSK->EVENT_TMR & GENFSK_EVENT_TMR_EVENT_TMR_MASK; in tmp_cb()
[all …]