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/Zephyr-latest/dts/bindings/rtc/
Dmicrocrystal,rv3028.yaml2 # SPDX-License-Identifier: Apache-2.0
9 - name: rtc-device.yaml
10 - name: i2c-device.yaml
13 clkout-frequency:
16 - 32768
17 - 8192
18 - 1024
19 - 64
20 - 32
21 - 1
[all …]
/Zephyr-latest/tests/drivers/build_all/rtc/
Di2c_devices.overlay3 * SPDX-License-Identifier: Apache-2.0
8 #address-cells = <1>;
9 #size-cells = <1>;
13 gpio-controller;
15 #gpio-cells = <0x2>;
20 #address-cells = <1>;
21 #size-cells = <0>;
25 clock-frequency = <100000>;
31 am1805-gpios = <&test_gpio 0 0>;
38 alarms-count = <1>;
[all …]
/Zephyr-latest/drivers/usb/udc/
Dudc_dwc2.c4 * SPDX-License-Identifier: Apache-2.0
44 /* Minimum RX FIFO size in 32-bit words considering the largest used OUT packet
49 /* Default Rx FIFO size in 32-bit words calculated to support High-Speed with:
50 * * 1 control endpoint in Completer/Buffer DMA mode: 13 locations
57 /* TX FIFO0 depth in 32-bit words (used by control IN endpoint)
105 /* Transfer triggers (IN on bits 0-15, OUT on bits 16-31) */
107 /* Finished transactions (IN on bits 0-15, OUT on bits 16-31) */
109 struct dwc2_reg_backup backup; member
143 const struct udc_dwc2_config *const config = dev->config; in dwc2_init_pinctrl()
144 const struct pinctrl_dev_config *const pcfg = config->pcfg; in dwc2_init_pinctrl()
[all …]
/Zephyr-latest/boards/st/nucleo_u5a5zj_q/doc/
Dindex.rst6 The Nucleo U5A5ZJ Q board, featuring an ARM Cortex-M33 based STM32U5A5ZJ MCU,
13 - STM32U5A5ZJ microcontroller in LQFP144 package
14 - Internal SMPS to generate V core logic supply
15 - Two types of extension resources:
17 - Arduino Uno V3 connectivity
18 - ST morpho extension pin headers for full access to all STM32 I/Os
20 - On-board ST-LINK/V3E debugger/programmer
21 - Flexible board power supply:
23 - USB VBUS or external source(3.3V, 5V, 7 - 12V)
24 - ST-Link V3E
[all …]
/Zephyr-latest/boards/st/b_u585i_iot02a/doc/
Dindex.rst6 The B_U585I_IOT02A Discovery kit features an ARM Cortex-M33 based STM32U585AI MCU
11 - STM32U585AII6Q microcontroller featuring 2 Mbyte of Flash memory, 786 Kbytes of RAM in UFBGA169 p…
12 - 512-Mbit octal-SPI Flash memory, 64-Mbit octal-SPI PSRAM, 256-Kbit I2C EEPROM
13 - USB FS, Sink and Source power, 2.5 W power capability
14 - 802.11 b/g/n compliant Wi-Fi® module from MXCHIP
15 - Bluetooth Low Energy from STMicroelectronics
16 - MEMS sensors from STMicroelectronics
18 - 2 digital microphones
19 - Relative humidity and temperature sensor
20 - 3-axis magnetometer
[all …]
/Zephyr-latest/drivers/gpio/
Dgpio_numicro.c4 * SPDX-License-Identifier: Apache-2.0
16 #include <zephyr/dt-bindings/gpio/numicro-gpio.h>
41 * backup of the INTEN register.
52 const struct gpio_numicro_config *cfg = dev->config; in gpio_numicro_configure()
53 GPIO_T * const regs = cfg->regs; in gpio_numicro_configure()
55 uint32_t mode; in gpio_numicro_configure() local
61 /* Pin mode */ in gpio_numicro_configure()
67 mode = GPIO_MODE_OPEN_DRAIN; in gpio_numicro_configure()
70 return -ENOTSUP; in gpio_numicro_configure()
73 mode = GPIO_MODE_OUTPUT; in gpio_numicro_configure()
[all …]
/Zephyr-latest/boards/st/nucleo_u575zi_q/doc/
Dindex.rst6 The Nucleo U575ZI Q board, featuring an ARM Cortex-M33 based STM32U575ZI MCU,
13 - STM32U575ZI microcontroller in LQFP144 package
14 - Internal SMPS to generate V core logic supply
15 - Two types of extension resources:
17 - Arduino Uno V3 connectivity
18 - ST morpho extension pin headers for full access to all STM32 I/Os
20 - On-board ST-LINK/V3E debugger/programmer
21 - Flexible board power supply:
23 - USB VBUS or external source(3.3V, 5V, 7 - 12V)
24 - ST-Link V3E
[all …]
/Zephyr-latest/subsys/net/lib/sockets/
Dsockets_inet.c6 * SPDX-License-Identifier: Apache-2.0
63 while ((p = k_fifo_get(&ctx->recv_q, K_NO_WAIT)) != NULL) { in zsock_flush_queue()
74 k_fifo_cancel_wait(&ctx->recv_q); in zsock_flush_queue()
77 (void)k_condvar_signal(&ctx->cond.recv); in zsock_flush_queue()
87 return -1; in zsock_socket_internal()
103 errno = -res; in zsock_socket_internal()
104 return -1; in zsock_socket_internal()
108 ctx->user_data = NULL; in zsock_socket_internal()
111 ctx->socket_data = NULL; in zsock_socket_internal()
114 k_fifo_init(&ctx->recv_q); in zsock_socket_internal()
[all …]
/Zephyr-latest/drivers/clock_control/
Dclock_control_esp32.c3 * Copyright (c) 2021-2024 Espressif Systems (Shanghai) Co., Ltd.
5 * SPDX-License-Identifier: Apache-2.0
16 #include <zephyr/dt-bindings/clock/esp32_clock.h>
22 #include <zephyr/dt-bindings/clock/esp32s2_clock.h>
28 #include <zephyr/dt-bindings/clock/esp32s3_clock.h>
33 #include <zephyr/dt-bindings/clock/esp32c2_clock.h>
37 #include <zephyr/dt-bindings/clock/esp32c3_clock.h>
41 #include <zephyr/dt-bindings/clock/esp32c6_clock.h>
386 * is used in a weird mode where clock to the peripheral is disabled but reset is also in esp32_clock_perip_init()
441 /* Force clear backup dma reset signal. This is a fix to the backup dma in esp32_clock_perip_init()
[all …]
Dclock_stm32_ll_u5.c6 * SPDX-License-Identifier: Apache-2.0
77 switch (LL_RCC_GetSysClkSource()) { in get_startup_frequency()
150 return -ENOTSUP; in enabled_clock()
161 if (IN_RANGE(pclken->bus, STM32_PERIPH_BUS_MIN, STM32_PERIPH_BUS_MAX) == 0) { in stm32_clock_control_on()
163 return -ENOTSUP; in stm32_clock_control_on()
166 sys_set_bits(DT_REG_ADDR(DT_NODELABEL(rcc)) + pclken->bus, in stm32_clock_control_on()
167 pclken->enr); in stm32_clock_control_on()
169 temp = sys_read32(DT_REG_ADDR(DT_NODELABEL(rcc)) + pclken->bus); in stm32_clock_control_on()
182 if (IN_RANGE(pclken->bus, STM32_PERIPH_BUS_MIN, STM32_PERIPH_BUS_MAX) == 0) { in stm32_clock_control_off()
184 return -ENOTSUP; in stm32_clock_control_off()
[all …]
Dclock_stm32_ll_wba.c4 * SPDX-License-Identifier: Apache-2.0
62 return -ENOTSUP; in enabled_clock()
73 if (IN_RANGE(pclken->bus, STM32_PERIPH_BUS_MIN, STM32_PERIPH_BUS_MAX) == 0) { in stm32_clock_control_on()
75 return -ENOTSUP; in stm32_clock_control_on()
78 sys_set_bits(DT_REG_ADDR(DT_NODELABEL(rcc)) + pclken->bus, in stm32_clock_control_on()
79 pclken->enr); in stm32_clock_control_on()
81 temp = sys_read32(DT_REG_ADDR(DT_NODELABEL(rcc)) + pclken->bus); in stm32_clock_control_on()
94 if (IN_RANGE(pclken->bus, STM32_PERIPH_BUS_MIN, STM32_PERIPH_BUS_MAX) == 0) { in stm32_clock_control_off()
96 return -ENOTSUP; in stm32_clock_control_off()
99 sys_clear_bits(DT_REG_ADDR(DT_NODELABEL(rcc)) + pclken->bus, in stm32_clock_control_off()
[all …]
Dclock_stm32_ll_common.c2 * Copyright (c) 2017-2022 Linaro Limited.
5 * SPDX-License-Identifier: Apache-2.0
76 #define RCC_PLLP_ENABLE() SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLPEN)
81 #define RCC_PLLQ_ENABLE() SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQEN)
124 switch (src_clk) { in enabled_clock()
136 r = -ENOTSUP; in enabled_clock()
150 r = -ENOTSUP; in enabled_clock()
157 r = -ENOTSUP; in enabled_clock()
164 r = -ENOTSUP; in enabled_clock()
171 r = -ENOTSUP; in enabled_clock()
[all …]
Dclock_stm32_ll_h7.c7 * SPDX-License-Identifier: Apache-2.0
205 switch (LL_RCC_PLL_GetSource()) { in get_pllsrc_frequency()
224 switch (LL_RCC_GetSysClkSource()) { in get_hclk_frequency()
339 return -ERANGE;
381 return -ENOTSUP;
392 if (IN_RANGE(pclken->bus, STM32_PERIPH_BUS_MIN, STM32_PERIPH_BUS_MAX) == 0) {
394 return -ENOTSUP;
399 sys_set_bits(STM32H7_BUS_CLK_REG + pclken->bus, pclken->enr);
403 temp = sys_read32(STM32H7_BUS_CLK_REG + pclken->bus);
418 if (IN_RANGE(pclken->bus, STM32_PERIPH_BUS_MIN, STM32_PERIPH_BUS_MAX) == 0) {
[all …]
/Zephyr-latest/drivers/counter/
Dcounter_gecko_rtcc.c4 * SPDX-License-Identifier: Apache-2.0
53 switch (chan_id) { in chan_id2cc_idx()
93 struct counter_gecko_data *const dev_data = dev->data; in counter_gecko_set_top_value()
99 const struct counter_gecko_config *const dev_cfg = dev->config; in counter_gecko_set_top_value()
101 if (dev_cfg->prescaler != 1) { in counter_gecko_set_top_value()
103 return -EINVAL; in counter_gecko_set_top_value()
109 if (dev_data->alarm[i].callback) { in counter_gecko_set_top_value()
110 return -EBUSY; in counter_gecko_set_top_value()
116 dev_data->top_callback = cfg->callback; in counter_gecko_set_top_value()
117 dev_data->top_user_data = cfg->user_data; in counter_gecko_set_top_value()
[all …]
/Zephyr-latest/boards/st/nucleo_wl55jc/doc/
Dnucleo_wl55jc.rst6 The NUCLEO-WL55JC STM32WL Nucleo-64 board provides an affordable and flexible
11 - STM32WL55JC microcontroller multiprotocol LPWAN dual-core 32-bit
12 (Arm® Cortex®-M4/M0+ at 48 MHz) in UFBGA73 package featuring:
14 - Ultra-low-power MCU
15 - RF transceiver (150 MHz to 960 MHz frequency range) supporting LoRa®,
17 - 256-Kbyte Flash memory and 64-Kbyte SRAM
19 - 3 user LEDs
20 - 3 user buttons and 1 reset push-button
21 - 32.768 kHz LSE crystal oscillator
22 - 32 MHz HSE on-board oscillator
[all …]
/Zephyr-latest/subsys/bluetooth/controller/
DKconfig.ll_sw_split3 # Copyright (c) 2016-2017 Nordic Semiconductor ASA
4 # SPDX-License-Identifier: Apache-2.0
120 # Hidden, Controller's Co-Operative high priority Rx thread stack size.
125 # Hidden, Controller's Co-Operative Rx thread stack size.
152 https://www.bluetooth.com/specifications/assigned-numbers/company-identifiers
162 bool "Legacy AD Data backup"
166 Backup Legacy Advertising Data when switching to Legacy Directed or
167 to Extended Advertising mode, and restore it when switching back to
168 Legacy Non-Directed Advertising mode.
170 Advertising or switch between Legacy and Extended Advertising.
[all …]
/Zephyr-latest/subsys/shell/
Dshell.c4 * SPDX-License-Identifier: Apache-2.0
47 sh->ctx->receive_state = state; in receive_state_change()
52 sh->ctx->cmd_buff[0] = '\0'; /* clear command buffer */ in cmd_buffer_clear()
53 sh->ctx->cmd_buff_pos = 0; in cmd_buffer_clear()
54 sh->ctx->cmd_buff_len = 0; in cmd_buffer_clear()
63 z_shell_help_cmd_print(sh, &sh->ctx->active_cmd); in shell_internal_help_print()
64 z_shell_help_subcmd_print(sh, &sh->ctx->active_cmd, in shell_internal_help_print()
76 * @return -EINVAL if wrong argument count
84 sh->ctx->active_cmd.syntax); in cmd_precheck()
90 return -EINVAL; in cmd_precheck()
[all …]
/Zephyr-latest/drivers/ieee802154/
Dieee802154_mcr20a.c1 /* ieee802154_mcr20a.c - NXP MCR20A driver */
8 * SPDX-License-Identifier: Apache-2.0
44 * Invalid for the SLOTTED mode.
99 /* Values for the power mode (PM) configuration */
113 #define MCR20A_OUTPUT_POWER_MIN (-35)
132 * Fc = 2405 + 5(k - 11) , k = 11,12,...,26
157 const struct mcr20a_config *config = dev->config; in z_mcr20a_read_reg()
178 if (spi_transceive_dt(&config->bus, &tx, &rx) == 0) { in z_mcr20a_read_reg()
179 return cmd_buf[len - 1]; in z_mcr20a_read_reg()
191 const struct mcr20a_config *config = dev->config; in z_mcr20a_write_reg()
[all …]
/Zephyr-latest/arch/x86/core/
Dx86_mmu.c2 * Copyright (c) 2011-2014 Wind River Systems, Inc.
3 * Copyright (c) 2017-2020 Intel Corporation
5 * SPDX-License-Identifier: Apache-2.0
28 /* We will use some ignored bits in the PTE to backup permission settings
29 * when the mapping was made. This is used to un-apply memory domain memory
43 * page table bit effecting the policy and also the backup bit.
51 * - If the entire entry is zero, it's an un-mapped virtual page
52 * - If PTE_ZERO is set, we flipped this page due to KPTI
53 * - Otherwise, this was a page-out
87 /* How many bits to right-shift a virtual address to obtain the
[all …]
/Zephyr-latest/drivers/usb/device/
Dusb_dc_sam_usbc.c4 * SPDX-License-Identifier: Apache-2.0
122 if (regs->UESTA[ep_idx] != dev_ep_sta_dbg[0][ep_idx]) { in usb_dc_sam_usbc_isr_sta_dbg()
123 dev_ep_sta_dbg[0][ep_idx] = regs->UESTA[ep_idx]; in usb_dc_sam_usbc_isr_sta_dbg()
128 regs->UDCON, regs->UDINT, regs->UDINTE, in usb_dc_sam_usbc_isr_sta_dbg()
129 regs->UECON[ep_idx], regs->UESTA[ep_idx], in usb_dc_sam_usbc_isr_sta_dbg()
136 regs->UDCON, regs->UDINT, regs->UDINTE, in usb_dc_sam_usbc_isr_sta_dbg()
137 regs->UECON[ep_idx], regs->UESTA[ep_idx]); in usb_dc_sam_usbc_isr_sta_dbg()
155 return USBC->USBCON & USBC_USBCON_FRZCLK; in usb_dc_sam_usbc_is_frozen_clk()
160 USBC->USBCON |= USBC_USBCON_FRZCLK; in usb_dc_sam_usbc_freeze_clk()
165 USBC->USBCON &= ~USBC_USBCON_FRZCLK; in usb_dc_sam_usbc_unfreeze_clk()
[all …]
/Zephyr-latest/doc/releases/
Drelease-notes-2.3.rst18 with future support for features like 64-bit and absolute timeouts in mind
21 * Zephyr now integrates with the TF-M (Trusted Firmware M) PSA-compliant
24 * The CMSIS-DSP library is now included and integrated
33 * CVE-2020-10022: UpdateHub Module Copies a Variable-Sized Hash String
34 into a fixed-size array.
35 * CVE-2020-10059: UpdateHub Module Explicitly Disables TLS
37 * CVE-2020-10061: Improper handling of the full-buffer case in the
39 * CVE-2020-10062: Packet length decoding error in MQTT
40 * CVE-2020-10063: Remote Denial of Service in CoAP Option Parsing Due
42 * CVE-2020-10068: In the Zephyr project Bluetooth subsystem, certain
[all …]
Drelease-notes-3.3.rst14 * Introduced :ref:`USB-C <usbc_api>` device stack with PD (power delivery)
17 CMSIS-DSP as the default backend.
30 * CVE-2023-0359: Under embargo until 2023-04-20
32 * CVE-2023-0779: Under embargo until 2023-04-22
66 removed in favor of new :dtcompatible:`zephyr,flash-disk` devicetree binding.
71 * Starting from this release ``zephyr-`` prefixed tags won't be created
82 image states). Use of a truncated hash or non-sha256 hash will still work
88 registration function at boot-up. If applications register this then
93 application code, these will now automatically be registered at boot-up (this
129 This may cause out-of-tree scripts or commands to fail if they have relied
[all …]
Drelease-notes-2.6.rst13 * Added support for 64-bit ARCv3
14 * Split ARM32 and ARM64, ARM64 is now a top-level architecture
15 * Added initial support for Arm v8.1-m and Cortex-M55
22 https://github.com/zephyrproject-rtos/example-application
34 * CVE-2021-3581: Under embargo until 2021-09-04
41 <https://github.com/zephyrproject-rtos/zephyr/issues?q=is%3Aissue+is%3Aopen+label%3Abug>`_.
46 * Driver APIs now return ``-ENOSYS`` if optional functions are not implemented.
47 If the feature is not supported by the hardware ``-ENOTSUP`` will be returned.
48 Formerly ``-ENOTSUP`` was returned for both failure modes, meaning this change
194 * Added support for null pointer dereferencing detection in Cortex-M.
[all …]
/Zephyr-latest/drivers/modem/
Dublox-sara-r4.c2 * Copyright (c) 2019-2020 Foundries.io
4 * SPDX-License-Identifier: Apache-2.0
209 int rc = -1; in find_apn()
219 s--; in find_apn()
223 s--; in find_apn()
231 s--; in find_apn()
237 int len = eos - s; in find_apn()
255 int rc = -1; in modem_detect_apn()
262 strncat(mmcmnc, imsi, sizeof(mmcmnc)-1); in modem_detect_apn()
303 struct sockaddr *dst_addr = msg->msg_name; in send_socket_data()
[all …]
/Zephyr-latest/boards/adi/max32662evkit/doc/
Dindex.rst6 the capabilities of the MAX32662 microcontroller, which is a cost-effective,
7 ultra-low power, highly integrated 32-bit microcontroller designed
8 for battery-powered edge devices.
15 - MAX32662 MCU:
17 - High-Efficiency Microcontroller for Low-Power High-Reliability Devices
19 - 256KB Flash
20 - 80KB SRAM, Optionally Preserved in LowestPower BACKUP Mode
21 - 16KB Unified Cache
22 - Memory Protection Unit (MPU)
23 - Dual- or Single-Supply Operation: 1.7V to 3.6V
[all …]

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