1.. zephyr:board:: max32662evkit 2 3Overview 4******** 5The MAX32662 evaluation kit (EV kit) provides a platform for evaluating 6the capabilities of the MAX32662 microcontroller, which is a cost-effective, 7ultra-low power, highly integrated 32-bit microcontroller designed 8for battery-powered edge devices. 9 10The Zephyr port is running on the MAX32662 MCU. 11 12Hardware 13******** 14 15- MAX32662 MCU: 16 17 - High-Efficiency Microcontroller for Low-Power High-Reliability Devices 18 19 - 256KB Flash 20 - 80KB SRAM, Optionally Preserved in LowestPower BACKUP Mode 21 - 16KB Unified Cache 22 - Memory Protection Unit (MPU) 23 - Dual- or Single-Supply Operation: 1.7V to 3.6V 24 - Wide Operating Temperature: -40°C to +105°C 25 26 - Flexible Clocking Schemes 27 28 - Internal High-Speed 100MHz 29 - Internal Low-Power 7.3728MHz 30 - Ultra-Low-Power 80kHz 31 - 16MHz–32MHz (External Crystal Required) 32 - 32.768kHz (External Crystal Required) 33 - External Clock Inputs for CPU and Low-PowerTimer 34 35 - Power Management Maximizes Uptime for Battery Applications 36 37 - 50μA/MHz at 0.9V up to 12MHz (CoreMark®) inACTIVE Mode 38 - 44μA/MHz at 1.1V up to 100MHz (While(1)) inACTIVE Mode 39 - 2.15μA Full Memory Retention Current in BACKUPMode at VDDIO = 1.8V 40 - 2.4μA Full Memory Retention Current in BACKUPMode at VDDIO = 3.3V 41 - 350nA Ultra-Low-Power RTC 42 - Wakeup from Low-Power Timer 43 44 - Optimal Peripheral Mix Provides Platform Scalability 45 46 - Up to 21 General-Purpose I/O Pins 47 - 4-Channel, 12-Bit, 1Msps ADC 48 - Two SPI Controller/Target 49 - One I2S Controller/Target 50 - Two 4-Wire UART 51 - Two I2C Controller/Target 52 - One CAN 2.0B Controller 53 - 4-Channel Standard DMA Controller 54 - Three 32-Bit Timers 55 - One 32-Bit Low-Power Timer 56 - One Watchdog Timer 57 - CMOS-Level 32.768kHz Calibration Output 58 - AES-128/192/256 Hardware Accelerator 59 60- Benefits and Features of MAX32662EVKIT: 61 62 - 3-Pin Terminal Block for CAN Bus 2.0B 63 - 128 x 128 (1.45in) Color TFT Display with SPI Interface 64 - Selectable On-Board High-Precision Voltage Reference 65 - USB 2.0 Micro-B to Serial UART 66 - All GPIOs Signals Accessed through 0.1in Headers 67 - Four Analog Inputs Accessed through 0.1in Header 68 - SWD 10-Pin Header 69 - Board Power Provided by USB Port 70 - On-Board LDO Regulators 71 - Individual Power Measurement on All IC Rails through Jumpers 72 - One General-Purpose LED 73 - One General-Purpose Pushbutton Switch 74 75Supported Features 76================== 77 78Below interfaces are supported by Zephyr on MAX32662EVKIT. 79 80+-----------+------------+-------------------------------------+ 81| Interface | Controller | Driver/Component | 82+===========+============+=====================================+ 83| NVIC | on-chip | nested vector interrupt controller | 84+-----------+------------+-------------------------------------+ 85| SYSTICK | on-chip | systick | 86+-----------+------------+-------------------------------------+ 87| CLOCK | on-chip | clock and reset control | 88+-----------+------------+-------------------------------------+ 89| GPIO | on-chip | gpio | 90+-----------+------------+-------------------------------------+ 91| UART | on-chip | serial | 92+-----------+------------+-------------------------------------+ 93| TRNG | on-chip | entropy | 94+-----------+------------+-------------------------------------+ 95| Watchdog | on-chip | watchdog | 96+-----------+------------+-------------------------------------+ 97| SPI | on-chip | spi | 98+-----------+------------+-------------------------------------+ 99| DMA | on-chip | dma controller | 100+-----------+------------+-------------------------------------+ 101| I2C | on-chip | i2c | 102+-----------+------------+-------------------------------------+ 103| ADC | on-chip | adc | 104+-----------+------------+-------------------------------------+ 105| Timer | on-chip | counter | 106+-----------+------------+-------------------------------------+ 107| PWM | on-chip | pwm | 108+-----------+------------+-------------------------------------+ 109| Flash | on-chip | flash | 110+-----------+------------+-------------------------------------+ 111 112Connections and IOs 113=================== 114 115+-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+ 116| Name | Name | Settings | Description | 117+===========+===============+===============+==================================================================================================+ 118| JP1 | VREF EN | | | 119| | | +-----------+ | +-------------------------------------------------------------------------------------------+ | 120| | | | 1-2 | | | Connects the external voltage reference to the VREF pin; must be enabled in the software. | | 121| | | | | | | See the External Voltage Reference (VREF) section for additional information. | | 122| | | +-----------+ | +-------------------------------------------------------------------------------------------+ | 123| | | | Open | | | Disconnects the external voltage reference. | | 124| | | +-----------+ | +-------------------------------------------------------------------------------------------+ | 125| | | | | 126+-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+ 127| JP2 | I2C1_SCL_PU | +-----------+ | +-------------------------------------------------------------------------------+ | 128| | | | 1-2 | | | Connects the pull-up to I2C1A_SCL (P0.6); sourced by V_AUX. | | 129| | | +-----------+ | +-------------------------------------------------------------------------------+ | 130| | | | Open | | | Disconnects the pull-up from I2C1A_SCL (P0.6); sourced by V_AUX. | | 131| | | +-----------+ | +-------------------------------------------------------------------------------+ | 132| | | | | 133+-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+ 134| JP3 | N/A | N/A | Does not exist. | 135+-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+ 136| JP4 | I2C1_SDA_PU | +-----------+ | +-------------------------------------------------------------------------------+ | 137| | | | 1-2 | | | Connects the pull-up to I2C1A_SDA (P0.9); sourced by V_AUX. | | 138| | | +-----------+ | +-------------------------------------------------------------------------------+ | 139| | | | Oepn | | | Disconnects the pull-up from I2C1A_SDA (P0.9); sourced by V_AUX. | | 140| | | +-----------+ | +-------------------------------------------------------------------------------+ | 141| | | | | 142+-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+ 143| JP5 | LED0 EN | +-----------+ | +-------------------------------------------------------------------------------+ | 144| | | | 1-2 | | | Enables LED0. | | 145| | | +-----------+ | +-------------------------------------------------------------------------------+ | 146| | | | Open | | | Disables LED0. | | 147| | | +-----------+ | +-------------------------------------------------------------------------------+ | 148| | | | | 149+-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+ 150| JP6 | CTS0A EN | +-----------+ | +-------------------------------------------------------------------------------+ | 151| | | | 1-2 | | | Connects the USB-to-serial bridge to UART0A_CTS (P0.20). | | 152| | | +-----------+ | +-------------------------------------------------------------------------------+ | 153| | | | Open | | | Disconnects the USB-to-serial bridge from UART0A_CTS (P0.20). | | 154| | | +-----------+ | +-------------------------------------------------------------------------------+ | 155| | | | | 156+-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+ 157| JP7 | RX0A EN | +-----------+ | +-------------------------------------------------------------------------------+ | 158| | | | 1-2 | | | Connects the USB-to-serial bridge to UART0A_RX (P0.11). | | 159| | | +-----------+ | +-------------------------------------------------------------------------------+ | 160| | | | Open | | | Disconnects the USB-to-serial bridge from UART0A_RX (P0.11). | | 161| | | +-----------+ | +-------------------------------------------------------------------------------+ | 162| | | | | 163+-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+ 164| JP8 | TX0A EN | +-----------+ | +-------------------------------------------------------------------------------+ | 165| | | | 1-2 | | | Connects the USB-to-serial bridge to UART0A_TX (P0.10). | | 166| | | +-----------+ | +-------------------------------------------------------------------------------+ | 167| | | | Open | | | Disconnects the USB-to-serial bridge from UART0A_TX (P0.10). | | 168| | | +-----------+ | +-------------------------------------------------------------------------------+ | 169| | | | | 170+-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+ 171| JP9 | RTS0A EN | +-----------+ | +-------------------------------------------------------------------------------+ | 172| | | | 1-2 | | | Connects the USB-to-serial bridge to UART0A_RTS (P0.19). | | 173| | | +-----------+ | +-------------------------------------------------------------------------------+ | 174| | | | Open | | | Disconnects the USB-to-serial bridge from UART0A_RTS (P0.19). | | 175| | | +-----------+ | +-------------------------------------------------------------------------------+ | 176| | | | | 177+-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+ 178| JP10 | VCORE EN | +-----------+ | +-------------------------------------------------------------------------------+ | 179| | | | 1-2 | | | Connects 1V1 to VCORE. | | 180| | | +-----------+ | +-------------------------------------------------------------------------------+ | 181| | | | Open | | | Disconnects 1V1 from VCORE. | | 182| | | +-----------+ | +-------------------------------------------------------------------------------+ | 183| | | | | 184+-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+ 185| JP11 | VDDIO/VDDASEL | +-----------+ | +-------------------------------------------------------------------------------+ | 186| | | | 2-1 | | | Connects 1V8 to V_AUX, VDDIO EN (JP12), and VDDA EN (JP13) jumpers. | | 187| | | +-----------+ | +-------------------------------------------------------------------------------+ | 188| | | | 2-3 | | | Connects 3V3 to V_AUX, VDDIO EN (JP12), and VDDA EN (JP13) jumpers. | | 189| | | +-----------+ | +-------------------------------------------------------------------------------+ | 190| | | | | 191+-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+ 192| JP12 | VDDIO EN | +-----------+ | +-------------------------------------------------------------------------------+ | 193| | | | 1-2 | | | Connects the JP11 selected voltage to VDDIO. | | 194| | | +-----------+ | +-------------------------------------------------------------------------------+ | 195| | | | Open | | | Disconnects the voltage from VDDIO. | | 196| | | +-----------+ | +-------------------------------------------------------------------------------+ | 197| | | | | 198+-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+ 199 200 201Programming and Debugging 202************************* 203 204Flashing 205======== 206 207An Arm® debug access port (DAP) provides an external interface for debugging during application 208development. The DAP is a standard Arm CoreSight® serial wire debug port, uses a two-pin serial 209interface (SWDCLK and SWDIO), and is accessed through 10-pin header (J3). Logic levels are set 210to V_AUX (1V8 or 3V3), which is determined by the shunt placement on JP11. In addition, 211the UART1A port can also be accessed through J3. 212 213 214Once the debug probe is connected to your host computer, then you can simply run the 215``west flash`` command to write a firmware image into flash. 216 217.. note:: 218 219 This board uses OpenOCD as the default debug interface. You can also use 220 a Segger J-Link with Segger's native tooling by overriding the runner, 221 appending ``--runner jlink`` to your ``west`` command(s). The J-Link should 222 be connected to the standard 2*5 pin debug connector (J3) using an 223 appropriate adapter board and cable. 224 225Debugging 226========= 227 228Please refer to the `Flashing`_ section and run the ``west debug`` command 229instead of ``west flash``. 230 231References 232********** 233 234- `MAX32662EVKIT web page`_ 235 236.. _MAX32662EVKIT web page: 237 https://www.analog.com/en/design-center/evaluation-hardware-and-software/evaluation-boards-kits/max32662evkit.html 238
