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/Zephyr-latest/dts/arm/st/f1/
Dstm32f103Xg.dtsi1 /* SPDX-License-Identifier: Apache-2.0
18 flash-controller@40022000 {
22 * This matters if you're doing in-application
24 * read-while-write capabilities, but is
25 * otherwise a non-issue.
28 erase-block-size = <DT_SIZE_K(2)>;
33 compatible = "st,stm32-timers";
35 clocks = <&rcc STM32_CLOCK(APB2, 19U)>;
36 resets = <&rctl STM32_RESET(APB2, 19U)>;
39 st,prescaler = <0>;
[all …]
Dstm32f103Xc.dtsi2 * Copyright (c) 2017 I-SENSE group of ICCS
7 * SPDX-License-Identifier: Apache-2.0
19 flash-controller@40022000 {
22 erase-block-size = <DT_SIZE_K(2)>;
27 compatible = "st,stm32-uart";
36 compatible = "st,stm32-uart";
45 compatible = "st,stm32-timers";
50 interrupt-names = "global";
51 st,prescaler = <0>;
55 compatible = "st,stm32-pwm";
[all …]
/Zephyr-latest/dts/bindings/clock/
Dnuvoton,npcm-pcc.yaml2 # SPDX-License-Identifier: Apache-2.0
8 High-Frequency Clock Generator (HFCG), is the source clock of Cortex-M4 core
14 clock-frequency = <DT_FREQ_M(96)>; /* OFMCLK runs at 96MHz */
15 core-prescaler = <1>; /* CORE_CLK runs at 96MHz */
16 apb1-prescaler = <8>; /* APB1_CLK runs at 12MHz */
17 apb2-prescaler = <1>; /* APB2_CLK runs at 96MHz */
18 apb3-prescaler = <1>; /* APB3_CLK runs at 96MHz */
19 apb6-prescaler = <1>; /* APB6_CLK runs at 96MHz */
20 fiu-prescaler = <1>; /* FIU_CLK runs at 96MHz */
21 i3c-prescaler = <1>; /* I3C_CLK runs at 96MHz */
[all …]
Dnuvoton,npcx-pcc.yaml2 # SPDX-License-Identifier: Apache-2.0
8 High-Frequency Clock Generator (HFCG), is the source clock of Cortex-M4 core
14 clock-frequency = <DT_FREQ_M(100)>; /* OFMCLK runs at 100MHz */
15 core-prescaler = <5>; /* CORE_CLK runs at 20MHz */
16 apb1-prescaler = <5>; /* APB1_CLK runs at 20MHz */
17 apb2-prescaler = <5>; /* APB2_CLK runs at 20MHz */
18 apb3-prescaler = <5>; /* APB3_CLK runs at 20MHz */
21 compatible: "nuvoton,npcx-pcc"
23 include: [clock-controller.yaml, base.yaml]
29 clock-frequency:
[all …]
Dst,stm32mp1-rcc.yaml2 # SPDX-License-Identifier: Apache-2.0
8 clock-frequency (mlhclk_ck).
10 compatible: "st,stm32mp1-rcc"
13 - name: st,stm32-rcc.yaml
14 property-blocklist:
15 - ahb-prescaler
16 - apb1-prescaler
17 - apb2-prescaler
18 - undershoot-prevention
Dst,stm32f1-rcc.yaml2 # SPDX-License-Identifier: Apache-2.0
6 Adds the ADC prescaler to the standard generic STM32 RCC.
7 For more description confere st,stm32-rcc.yaml
9 compatible: "st,stm32f1-rcc"
11 include: st,stm32-rcc.yaml
14 adc-prescaler:
17 - 2
18 - 4
19 - 6
20 - 8
[all …]
Dst,stm32wba-rcc.yaml2 # SPDX-License-Identifier: Apache-2.0
13 Core clock frequency should also be defined, using "clock-frequency" property.
15 Core clock frequency = SYSCLK / AHB prescaler
17 matching prescaler properties.
21 ahb-prescaler = <2>;
22 clock-frequency = <DT_FREQ_M(40)>; /* = SYSCLK / AHB prescaler */
23 apb1-presacler = <1>;
24 apb2-presacler = <1>;
25 apb7-presacler = <7>;
55 compatible: "st,stm32wba-rcc"
[all …]
/Zephyr-latest/tests/drivers/clock_control/stm32_clock_configuration/stm32u5_devices/boards/
Dcore_init.overlay4 * SPDX-License-Identifier: Apache-2.0
19 /delete-property/ clock-frequency;
20 /delete-property/ hse-bypass;
33 /delete-property/ msi-range;
34 /delete-property/ msi-pll-mode;
39 /delete-property/ msi-range;
40 /delete-property/ msi-pll-mode;
44 /delete-property/ div-m;
45 /delete-property/ mul-n;
46 /delete-property/ div-q;
[all …]
/Zephyr-latest/tests/drivers/clock_control/stm32_clock_configuration/stm32wba_core/boards/
Dhse_32.overlay4 * SPDX-License-Identifier: Apache-2.0
18 clock-frequency = <DT_FREQ_M(32)>;
19 ahb-prescaler = <1>;
20 ahb5-prescaler = <1>;
21 apb1-prescaler = <1>;
22 apb2-prescaler = <1>;
23 apb7-prescaler = <1>;
Dhse_16.overlay4 * SPDX-License-Identifier: Apache-2.0
14 hse-div2;
19 clock-frequency = <DT_FREQ_M(16)>;
20 ahb-prescaler = <1>;
21 apb1-prescaler = <1>;
22 apb2-prescaler = <1>;
23 apb7-prescaler = <1>;
Dhsi_16_ahb5_div.overlay4 * SPDX-License-Identifier: Apache-2.0
18 clock-frequency = <DT_FREQ_M(16)>;
19 ahb-prescaler = <1>;
20 ahb5-div;
21 apb1-prescaler = <1>;
22 apb2-prescaler = <1>;
23 apb7-prescaler = <1>;
Dhsi_16.overlay4 * SPDX-License-Identifier: Apache-2.0
18 clock-frequency = <DT_FREQ_M(16)>;
19 ahb-prescaler = <1>;
20 apb1-prescaler = <1>;
21 apb2-prescaler = <1>;
22 apb7-prescaler = <1>;
Dpll_hse_100.overlay4 * SPDX-License-Identifier: Apache-2.0
14 clock-frequency = <DT_FREQ_M(32)>;
18 div-m = <8>;
19 mul-n = <100>;
20 div-q = <2>;
21 div-r = <4>;
28 clock-frequency = <DT_FREQ_M(100)>;
29 ahb-prescaler = <1>;
30 ahb5-prescaler = <4>;
31 apb1-prescaler = <1>;
[all …]
Dpll_hse_100_ahb_50.overlay4 * SPDX-License-Identifier: Apache-2.0
14 clock-frequency = <DT_FREQ_M(32)>;
18 div-m = <8>;
19 mul-n = <100>;
20 div-q = <2>;
21 div-r = <4>;
28 ahb-prescaler = <2>;
29 clock-frequency = <DT_FREQ_M(50)>;
30 ahb5-prescaler = <4>;
31 apb1-prescaler = <1>;
[all …]
/Zephyr-latest/tests/drivers/clock_control/stm32_clock_configuration/stm32u5_core/boards/
Dhsi_16.overlay4 * SPDX-License-Identifier: Apache-2.0
18 clock-frequency = <DT_FREQ_M(16)>;
19 ahb-prescaler = <1>;
20 apb1-prescaler = <1>;
21 apb2-prescaler = <1>;
22 apb3-prescaler = <1>;
Dmsis_24.overlay4 * SPDX-License-Identifier: Apache-2.0
18 msi-range = <1>;
19 msi-pll-mode;
24 clock-frequency = <DT_FREQ_M(24)>;
25 ahb-prescaler = <1>;
26 apb1-prescaler = <1>;
27 apb2-prescaler = <1>;
28 apb3-prescaler = <1>;
Dmsis_48.overlay4 * SPDX-License-Identifier: Apache-2.0
18 msi-range = <0>;
19 msi-pll-mode;
24 clock-frequency = <DT_FREQ_M(48)>;
25 ahb-prescaler = <1>;
26 apb1-prescaler = <1>;
27 apb2-prescaler = <1>;
28 apb3-prescaler = <1>;
Dpll_hsi_160.overlay4 * SPDX-License-Identifier: Apache-2.0
17 div-m = <4>;
18 mul-n = <40>;
19 div-q = <2>;
20 div-r = <1>;
27 clock-frequency = <DT_FREQ_M(160)>;
28 ahb-prescaler = <1>;
29 apb1-prescaler = <1>;
30 apb2-prescaler = <1>;
31 apb3-prescaler = <1>;
Dpll_hsi_40.overlay4 * SPDX-License-Identifier: Apache-2.0
17 div-m = <4>;
18 mul-n = <10>;
19 div-q = <2>;
20 div-r = <1>;
27 clock-frequency = <DT_FREQ_M(40)>;
28 ahb-prescaler = <1>;
29 apb1-prescaler = <1>;
30 apb2-prescaler = <1>;
31 apb3-prescaler = <1>;
Dhse_16.overlay4 * SPDX-License-Identifier: Apache-2.0
19 clock-frequency = <DT_FREQ_M(16)>;
20 hse-bypass;
25 clock-frequency = <DT_FREQ_M(16)>;
26 ahb-prescaler = <1>;
27 apb1-prescaler = <1>;
28 apb2-prescaler = <1>;
29 apb3-prescaler = <1>;
Dpll_msis_ahb_2_40.overlay4 * SPDX-License-Identifier: Apache-2.0
18 msi-range = <4>;
19 msi-pll-mode;
23 div-m = <1>;
24 mul-n = <80>;
25 div-q = <4>;
26 div-r = <4>;
33 ahb-prescaler = <2>; /* Use AHB prescaler to reduce HCLK */
34 clock-frequency = <DT_FREQ_M(40)>;
35 apb1-prescaler = <1>;
[all …]
/Zephyr-latest/tests/drivers/clock_control/stm32_clock_configuration/stm32h5_core/boards/
Dcsi4.overlay5 * SPDX-License-Identifier: Apache-2.0
19 clock-frequency = <DT_FREQ_M(4)>;
20 ahb-prescaler = <1>;
21 apb1-prescaler = <1>;
22 apb2-prescaler = <1>;
23 apb3-prescaler = <1>;
Dhse24.overlay5 * SPDX-License-Identifier: Apache-2.0
20 clock-frequency = <DT_FREQ_M(24)>;
25 clock-frequency = <DT_FREQ_M(24)>;
26 ahb-prescaler = <1>;
27 apb1-prescaler = <1>;
28 apb2-prescaler = <1>;
29 apb3-prescaler = <1>;
Dpll_csi_ahb_2_100.overlay5 * SPDX-License-Identifier: Apache-2.0
18 div-m = <1>;
19 mul-n = <100>;
20 div-p = <2>;
21 div-q = <2>;
22 div-r = <2>;
29 ahb-prescaler = <2>; /* Use AHB prescaler to reduce HCLK */
30 clock-frequency = <DT_FREQ_M(100)>;
31 apb1-prescaler = <1>;
32 apb2-prescaler = <1>;
[all …]
/Zephyr-latest/tests/drivers/clock_control/stm32_clock_configuration/stm32_common_core/boards/
Df2_f4_f7_pll_100_hsi_16_ahb_2.overlay4 * SPDX-License-Identifier: Apache-2.0
17 div-m = <8>;
18 mul-n = <200>;
19 div-p = <4>;
26 ahb-prescaler = <2>;
27 clock-frequency = <DT_FREQ_M(50)>; /* Pll Output (100) / AHB prescaler */
28 apb1-prescaler = <2>;
29 apb2-prescaler = <2>;

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