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/Zephyr-latest/samples/subsys/zbus/priority_boost/
Dsample.yaml10 - "I: 0 -> T1: prio before 5"
11 - "I: 0 ---> L1: T1 prio 5"
12 - "I: 0 ---> L2: T1 prio 5"
13 - "I: 0 -> T1: prio after 5"
14 - "I: 1 -> T1: prio before 5"
15 - "I: 1 ---> L1: T1 prio 5"
16 - "I: 1 ---> L2: T1 prio 5"
17 - "I: 1 -> T1: prio after 5"
18 - "I: 2 -> T1: prio before 5"
19 - "I: 2 ---> L1: T1 prio 5"
[all …]
DREADME.rst62 I: 0 -> T1: prio before 5
63 I: 0 ---> L1: T1 prio 5
64 I: 0 -> MS1: T1 prio 5
65 I: 0 -> MS2: T1 prio 5
66 I: 0 ---> L2: T1 prio 5
67 I: 0 -> T1: prio after 5
68 I: N -> S1: T1 prio 5
69 I: 0 -> S1: T1 prio 5
71 I: 1 -> T1: prio before 5
72 I: 1 ---> L1: T1 prio 5
[all …]
/Zephyr-latest/tests/kernel/fpu_sharing/generic/src/
Dfloat_regs_riscv_gcc.h52 "mv t1, %1\n" in _load_all_float_registers()
54 "add t0, t0, t1\n" in _load_all_float_registers()
56 "add t0, t0, t1\n" in _load_all_float_registers()
58 "add t0, t0, t1\n" in _load_all_float_registers()
60 "add t0, t0, t1\n" in _load_all_float_registers()
62 "add t0, t0, t1\n" in _load_all_float_registers()
64 "add t0, t0, t1\n" in _load_all_float_registers()
66 "add t0, t0, t1\n" in _load_all_float_registers()
68 "add t0, t0, t1\n" in _load_all_float_registers()
70 "add t0, t0, t1\n" in _load_all_float_registers()
[all …]
/Zephyr-latest/arch/riscv/core/
Disr.S28 RV_E( op t1, __struct_arch_esf_t1_OFFSET(sp) );\
143 /* preserve t0 and t1 temporarily */
145 sr t1, _curr_cpu_arch_user_exc_tmp1(s0)
149 li t1, MSTATUS_MPP
150 and t0, t0, t1
181 /* retrieve original t0/t1 values */
183 lr t1, _curr_cpu_arch_user_exc_tmp1(s0)
211 li t1, MSTATUS_FS
212 and t1, t1, t2
213 bnez t1, no_fp
[all …]
Dreset.S66 li t1, __z_interrupt_all_stacks_SIZEOF
67 add t1, t1, t0
74 blt t0, t1, aa_loop
98 li t1, -1
99 sr t1, 0(t0)
113 li t1, 1
114 sr t1, 0(t0)
Dpmp.S40 slli t1, a0, 4 /* 16-byte instruction blocks */
41 add t0, t0, t1
51 li t1, _index + 1
53 beq t1, a1, pmpaddr_done
67 slli t1, a0, 4 /* 16-byte instruction blocks */
68 add t0, t0, t1
/Zephyr-latest/soc/openisa/rv32m1/
Dsoc_irq.S34 li t1, 1
35 sll t1, t1, a0
36 sw t1, 0x00(t0)
53 csrr t1, RI5CY_LPEND0
56 sw t1, __soc_esf_t_lpend0_OFFSET(a0)
59 csrr t1, RI5CY_LPEND1
62 sw t1, __soc_esf_t_lpend1_OFFSET(a0)
71 lw t1, __soc_esf_t_lpend0_OFFSET(a0)
74 csrw RI5CY_LPEND0, t1
77 lw t1, __soc_esf_t_lpend1_OFFSET(a0)
[all …]
Dwdog.S45 li t1, WDOG_BASE
49 sw t2, WDOG_CNT_OFFSET(t1)
52 lw t2, WDOG_CS_OFFSET(t1)
55 sw t2, WDOG_CS_OFFSET(t1)
59 sw t2, WDOG_TOVAL_OFFSET(t1)
/Zephyr-latest/soc/ite/ec/common/
Dvector.S32 lb t1, 0(t0)
33 ori t1, t1, IT8XXX2_GCTRL_JTAG
34 sb t1, 0(t0)
37 li t1, 0
39 sb t1, 0(t0)
41 sb t1, 1(t0)
43 sb t1, 4(t0)
45 sb t1, 5(t0)
47 sb t1, 6(t0)
51 sb t1, 0(t0)
[all …]
/Zephyr-latest/arch/mips/core/
Disr.S44 op t1, ESF_O(t1)(sp) ;\
91 mflo t1
93 OP_STOREREG t1, ESF_O(lo)(sp)
96 mfc0 t1, CP0_BADVADDR
97 OP_STOREREG t1, ESF_O(badvaddr)(sp)
100 mfc0 t1, CP0_CAUSE
101 OP_STOREREG t1, ESF_O(cause)(sp)
107 and k1, k0, t1
115 and t1, t1, t0
117 and a0, a0, t1
[all …]
Dreset.S35 li t1, CONFIG_ISR_STACK_SIZE
36 add t1, t1, t0
43 blt t0, t1, aa_loop
/Zephyr-latest/soc/telink/tlsr/tlsr951x/
Dstart.S56 la t1, _RETENTION_DATA_LMA_START
61 lw t0, 0(t1)
63 addi t1, t1, 4
68 la t1, _RAMCODE_LMA_START
73 lw t0, 0(t1)
75 addi t1, t1, 4
Dsoc_irq.S28 csrr t1, ucode
35 sw t1, __soc_esf_t_ucode_OFFSET(a0)
45 lw t1, __soc_esf_t_ucode_OFFSET(a0)
52 csrw ucode, t1
/Zephyr-latest/tests/kernel/ipi_cascade/src/
Dmain.c14 * Thread T1 (main thread) starts on core X at a med-high priority.
19 * T1 (main thread) locks interrupts to force it to be last to service any IPIs.
22 * T1 unlocks interrupts, processes the IPI and T3 runs on core X.
24 * Since T1 is of higher priority than T4, T4 should get switched out for T1
25 * leaving T3 and T1 executing on the 2 CPUs. However, this final step will
92 * (T1/test_ipi_cascade) will verify that the timer did not execute.
103 /* T3 executes at PRIORITY_HIGH - will get pinned to T1's CPU */
117 /* 9.1 - T3 should be executing on the same CPU that T1 was. */ in thread3_entry()
121 zassert_true(cpu_t3 == cpu_t1, "T3 not executing on T1's original CPU"); in thread3_entry()
146 * Due to the IPI cascades, T4 will get switched out for T1. in thread4_entry()
[all …]
/Zephyr-latest/tests/net/trickle/src/
Dmain.c62 static struct net_trickle t1; variable
89 ret = net_trickle_create(&t1, T1_IMIN, T1_IMAX, T1_K); in test_trickle_create()
103 ret = net_trickle_start(&t1, cb_1, &t1); in test_trickle_start()
112 zassert_false(net_trickle_stop(&t1), in test_trickle_stop()
121 zassert_true(net_trickle_is_running(&t1), "Trickle 1 not running"); in test_trickle_1_status()
124 net_trickle_inconsistency(&t1); in test_trickle_1_status()
126 net_trickle_consistency(&t1); in test_trickle_1_status()
147 zassert_true(net_trickle_is_running(&t1), "Trickle 1 not running"); in test_trickle_1_wait()
159 zassert_true(net_trickle_is_running(&t1), "Trickle 1 not running"); in test_trickle_1_wait_long()
179 zassert_false(net_trickle_is_running(&t1), "Trickle 1 running"); in test_trickle_1_stopped()
[all …]
/Zephyr-latest/soc/neorv32/
Dsoc_irq.S21 li t1, 1
22 sll t0, t1, a0
24 and t1, t2, t0
25 csrrs t2, mie, t1
/Zephyr-latest/soc/nordic/common/vpr/
Dsoc_isr_stacking.h29 unsigned long t1; \
51 unsigned long t1; \
93 addi t1, sp, __struct_arch_esf_soc_context_OFFSET; \
96 sr t0, __soc_esf_t_sp_align_OFFSET(t1)
99 addi t1, sp, __struct_arch_esf_soc_context_OFFSET; \
100 lr t0, __soc_esf_t_sp_align_OFFSET(t1); \
101 lr t1, __struct_arch_esf_mepc_OFFSET(sp); \
102 or t2, t1, t0; \
/Zephyr-latest/soc/andestech/ae350/
Dsoc_irq.S24 csrr t1, NDS_UCODE
31 sw t1, __soc_esf_t_ucode_OFFSET(a0)
41 lw t1, __soc_esf_t_ucode_OFFSET(a0)
48 csrw NDS_UCODE, t1
Dstart.S43 li t1, (1 << 19)
44 and t0, t0, t1
48 li t1, (1 << 20)
51 and t0, t0, t1
/Zephyr-latest/include/zephyr/net/
Dmdio.h108 /* BASE-T1 registers */
109 /** BASE-T1 Auto-negotiation control */
111 /** BASE-T1 Auto-negotiation status */
113 /** BASE-T1 Auto-negotiation advertisement register [15:0] */
115 /** BASE-T1 Auto-negotiation advertisement register [31:16] */
117 /** BASE-T1 Auto-negotiation advertisement register [47:32] */
119 /** BASE-T1 PMA/PMD control register */
122 /* BASE-T1 Auto-negotiation Control register */
128 /* BASE-T1 Auto-negotiation Status register */
140 /* BASE-T1 Auto-negotiation Advertisement register [15:0] */
[all …]
/Zephyr-latest/tests/subsys/fs/littlefs/src/
Dtest_lfs_perf.c34 uint32_t t1; in write_read() local
95 t1 = k_uptime_get_32(); in write_read()
97 if (t1 == t0) { in write_read()
98 t1++; in write_read()
116 tag, nbuf, buf_size, total, (t1 - t0), in write_read()
117 (uint32_t)(total * 1000U / (t1 - t0)), in write_read()
118 (uint32_t)(total * 1000U / (t1 - t0) / 1024U)); in write_read()
134 t1 = k_uptime_get_32(); in write_read()
136 if (t1 == t0) { in write_read()
137 t1++; in write_read()
[all …]
/Zephyr-latest/tests/kernel/tickless/tickless_concept/src/
Dmain.c71 volatile uint32_t t0, t1; in ZTEST() local
76 t1 = k_uptime_get_32(); in ZTEST()
77 TC_PRINT("time %d, %d\n", t0, t1); in ZTEST()
79 zassert_true((t1 - t0) >= SLEEP_TICKLESS); in ZTEST()
84 t1 = k_uptime_get_32(); in ZTEST()
85 TC_PRINT("time %d, %d\n", t0, t1); in ZTEST()
87 zassert_true((t1 - t0) >= SLEEP_TICKFUL); in ZTEST()
/Zephyr-latest/samples/subsys/zbus/priority_boost/src/
Dmain.c38 LOG_INF("N -> S1: T1 prio %d", k_thread_priority_get(t1_id)); in s1_thread()
44 LOG_INF("%d -> S1: T1 prio %d", a, k_thread_priority_get(t1_id)); in s1_thread()
71 LOG_INF("%d -> MS1: T1 prio %d", a, k_thread_priority_get(t1_id)); in ms1_thread()
98 LOG_INF("%d -> MS2: T1 prio %d", a, k_thread_priority_get(t1_id)); in ms2_thread()
105 LOG_INF("%d ---> L1: T1 prio %d", *((int *)zbus_chan_const_msg(chan)), in l1_callback()
112 LOG_INF("%d ---> L2: T1 prio %d", *((int *)zbus_chan_const_msg(chan)), in l2_callback()
138 LOG_INF("%d -> T1: prio before %d", a, k_thread_priority_get(k_current_get())); in t1_thread()
143 LOG_INF("%d -> T1: prio after %d", a, k_thread_priority_get(k_current_get())); in t1_thread()
/Zephyr-latest/soc/common/riscv-privileged/
Dsoc_irq.S29 li t1, 1
30 sll t0, t1, a0
31 csrrc t1, mip, t0
/Zephyr-latest/dts/bindings/led_strip/
Dworldsemi,ws2812-rpi_pico-pio.yaml19 The T1 is equal to (T1H-T0H) or (T0L-T1L) in the datasheet.
24 | T0 | T1+T2 |
31 | T0+T1 | T2 |
39 For example, T0=3, T1=3, T2=4 and the frequency is 800kHz case,

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