1/*
2 * Copyright (c) 2021 Andes Technology Corporation
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7#include "soc_v5.h"
8
9#include <zephyr/toolchain.h>
10
11/* exports */
12GTEXT(entry)
13
14SECTION_FUNC(init, entry)
15	/* Disable linker relaxation before GP register initialization. */
16	.option push
17	.option norelax
18
19#ifdef CONFIG_SOC_ANDES_V5_EXECIT
20	/* Initialize EXECIT table */
21	la t0, _ITB_BASE_
22	csrw NDS_UITB, t0
23#endif
24
25#ifdef CONFIG_ICACHE
26	/* Enable I cache with HW prefetcher. */
27	li t0, (1 << 9) | (1 << 0)
28	csrs NDS_MCACHE_CTL, t0
29#endif
30
31#ifdef CONFIG_DCACHE
32	/*
33	 * Enable D cache with HW prefetcher, D-cache write-around
34	 * (threshold: 4 cache lines), and CM (Coherence Manager).
35	 */
36	li t0, (0x3 << 13)
37	csrc NDS_MCACHE_CTL, t0
38	li t0, (1 << 19) | (1 << 13) | (1 << 10) | (1 << 1)
39	csrs NDS_MCACHE_CTL, t0
40
41	/* Check if CPU support CM or not. */
42	csrr t0, NDS_MCACHE_CTL
43	li t1, (1 << 19)
44	and t0, t0, t1
45	beqz t0, cache_enable_finish
46
47	/* If CPU support CM, check if CM is enabled. */
48	li t1, (1 << 20)
49check_cm_enabled:
50	csrr t0, NDS_MCACHE_CTL
51	and t0, t0, t1
52	beqz t0, check_cm_enabled
53
54cache_enable_finish:
55#endif
56
57	/* Enable misaligned access and non-blocking load */
58	li t0, (1 << 8) | (1 << 6)
59	csrs NDS_MMISC_CTL, t0
60
61	j __start
62
63	.option pop
64