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/Zephyr-latest/tests/kernel/fpu_sharing/generic/src/
Dfloat_regs_riscv_gcc.h51 "mv t0, %0\n" in _load_all_float_registers()
53 RV_FPREG_LOAD "f0, 0(t0)\n" in _load_all_float_registers()
54 "add t0, t0, t1\n" in _load_all_float_registers()
55 RV_FPREG_LOAD "f1, 0(t0)\n" in _load_all_float_registers()
56 "add t0, t0, t1\n" in _load_all_float_registers()
57 RV_FPREG_LOAD "f2, 0(t0)\n" in _load_all_float_registers()
58 "add t0, t0, t1\n" in _load_all_float_registers()
59 RV_FPREG_LOAD "f3, 0(t0)\n" in _load_all_float_registers()
60 "add t0, t0, t1\n" in _load_all_float_registers()
61 RV_FPREG_LOAD "f4, 0(t0)\n" in _load_all_float_registers()
[all …]
/Zephyr-latest/arch/riscv/core/
Dreset.S42 li t0, CONFIG_RV_BOOT_HART
43 beq a0, t0, boot_first_core
52 li t0, MSTATUS_FS_INIT
53 csrs mstatus, t0
64 la t0, z_interrupt_stacks
67 add t1, t1, t0
72 sw t2, 0x00(t0)
73 addi t0, t0, 4
74 blt t0, t1, aa_loop
82 li t0, __z_interrupt_stack_SIZEOF
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Disr.S27 RV_E( op t0, __struct_arch_esf_t0_OFFSET(sp) );\
143 /* preserve t0 and t1 temporarily */
144 sr t0, _curr_cpu_arch_user_exc_tmp0(s0)
148 csrr t0, mstatus
150 and t0, t0, t1
151 bnez t0, 1f
154 mv t0, sp
160 sr t0, (-__struct_arch_esf_SIZEOF + __struct_arch_esf_sp_OFFSET)(sp)
163 lr t0, ___cpu_t_current_OFFSET(s0)
164 lr tp, _thread_offset_to_tls(t0)
[all …]
Dpmp.S39 la t0, pmpaddr_store
41 add t0, t0, t1
42 jr t0
50 lr t0, (RV_REGSIZE * _index)(a3)
52 csrw (CSR_PMPADDR_BASE + _index), t0
65 la t0, pmpcfg_store
68 add t0, t0, t1
71 jr t0
79 lr t0, (RV_REGSIZE * _index)(a4)
81 csrw (CSR_PMPCFG_BASE + RV_REGSIZE/4 * _index), t0
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Dfpu.S57 frcsr t0
59 sw t0, __z_riscv_fp_context_t_fcsr_OFFSET(a0)
66 lw t0, __z_riscv_fp_context_t_fcsr_OFFSET(a0)
67 fscsr t0
/Zephyr-latest/soc/andestech/ae350/
Dstart.S21 la t0, _ITB_BASE_
22 csrw NDS_UITB, t0
27 li t0, (1 << 9) | (1 << 0)
28 csrs NDS_MCACHE_CTL, t0
36 li t0, (0x3 << 13)
37 csrc NDS_MCACHE_CTL, t0
38 li t0, (1 << 19) | (1 << 13) | (1 << 10) | (1 << 1)
39 csrs NDS_MCACHE_CTL, t0
42 csrr t0, NDS_MCACHE_CTL
44 and t0, t0, t1
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Dsoc_irq.S21 csrr t0, NDS_MXSTATUS
28 sw t0, __soc_esf_t_mxstatus_OFFSET(a0)
38 lw t0, __soc_esf_t_mxstatus_OFFSET(a0)
45 csrw NDS_MXSTATUS, t0
/Zephyr-latest/soc/telink/tlsr/tlsr951x/
Dstart.S35 csrr t0, NDS_MCACHE_CTL
36 ori t0, t0, 1 #/I-Cache
37 ori t0, t0, 2 #/D-Cache
38 csrw NDS_MCACHE_CTL, t0
42 li t0, (1 << 8) | (1 << 6)
43 csrs NDS_MMISC_CTL, t0
46 lui t0, 0
51 sw t0, 0(t2)
61 lw t0, 0(t1)
62 sw t0, 0(t2)
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Dsoc_irq.S25 csrr t0, NDS_MXSTATUS
32 sw t0, __soc_esf_t_mxstatus_OFFSET(a0)
42 lw t0, __soc_esf_t_mxstatus_OFFSET(a0)
49 csrw NDS_MXSTATUS, t0
/Zephyr-latest/soc/nordic/common/vpr/
Dsoc_isr_stacking.h28 unsigned long t0; \
52 unsigned long t0; \
94 lr t0, __struct_arch_esf_mepc_OFFSET(sp); \
95 andi t0, t0, MEPC_SP_ALIGN_BIT_MASK; \
96 sr t0, __soc_esf_t_sp_align_OFFSET(t1)
100 lr t0, __soc_esf_t_sp_align_OFFSET(t1); \
102 or t2, t1, t0; \
106 csrw mscratch, t0; \
108 csrr t0, mcause; \
109 srli t0, t0, RISCV_MCAUSE_IRQ_POS; \
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Dsoc_context.S13 csrr t0, 0x347
14 sw t0, __soc_esf_t_minttresh_OFFSET(a0)
19 lw t0, __soc_esf_t_minttresh_OFFSET(a0)
20 csrw 0x347, t0
/Zephyr-latest/soc/common/riscv-privileged/
Dvector.S41 la t0, _isr_wrapper
43 add t0, zero, zero
45 addi t0, t0, 0x03 /* Enable CLIC vectored mode by setting LSB */
46 csrw mtvec, t0
60 la t0, _irq_vector_table
61 csrw 0x307, t0 /* mtvt */
77 la t0, _irq_vector_table /* Load address of interrupt vector table */
78 addi t0, t0, 0x01 /* Enable vectored mode by setting LSB */
79 csrw mtvec, t0
87 la t0, _isr_wrapper
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/Zephyr-latest/include/zephyr/arch/riscv/
Dsyscall.h50 register unsigned long t0 __asm__ ("t0") = call_id; in arch_syscall_invoke6()
55 "r" (t0) in arch_syscall_invoke6()
70 register unsigned long t0 __asm__ ("t0") = call_id; in arch_syscall_invoke5()
74 : "r" (a1), "r" (a2), "r" (a3), "r" (a4), "r" (t0) in arch_syscall_invoke5()
87 register unsigned long t0 __asm__ ("t0") = call_id; in arch_syscall_invoke4()
91 : "r" (a1), "r" (a2), "r" (a3), "r" (t0) in arch_syscall_invoke4()
103 register unsigned long t0 __asm__ ("t0") = call_id; in arch_syscall_invoke3()
107 : "r" (a1), "r" (a2), "r" (t0) in arch_syscall_invoke3()
117 register unsigned long t0 __asm__ ("t0") = call_id; in arch_syscall_invoke2()
121 : "r" (a1), "r" (t0) in arch_syscall_invoke2()
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/Zephyr-latest/soc/openisa/rv32m1/
Dsoc_irq.S33 la t0, __EVENT_INTPTPENDCLEAR
36 sw t1, 0x00(t0)
52 csrr t0, RI5CY_LPSTART0
55 sw t0, __soc_esf_t_lpstart0_OFFSET(a0)
58 csrr t0, RI5CY_LPSTART1
61 sw t0, __soc_esf_t_lpstart1_OFFSET(a0)
70 lw t0, __soc_esf_t_lpstart0_OFFSET(a0)
73 csrw RI5CY_LPSTART0, t0
76 lw t0, __soc_esf_t_lpstart1_OFFSET(a0)
79 csrw RI5CY_LPSTART1, t0
/Zephyr-latest/soc/ite/ec/common/
Dvector.S31 la t0, IT8XXX2_GCTRL_PMER3
32 lb t1, 0(t0)
34 sb t1, 0(t0)
36 la t0, IT8XXX2_JTAG_PINS_BASE
39 sb t1, 0(t0)
41 sb t1, 1(t0)
43 sb t1, 4(t0)
45 sb t1, 5(t0)
47 sb t1, 6(t0)
50 la t0, IT8XXX2_JTAG_VOLT_SET
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/Zephyr-latest/samples/kernel/metairq_dispatch/
DREADME.rst96 II: M0 T0 mirq 4478 disp 7478 proc 24336 real 24613
97 I: M8 T0 mirq 4273 disp 86983 proc 9824 real 16753
98 I: M10 T0 mirq 4273 disp 495455 proc 21177 real 28273
99 I: M11 T0 mirq 4273 disp 981565 proc 48337 real 48918
100 I: M14 T0 mirq 4273 disp 1403627 proc 7079 real 7690
101 I: M17 T0 mirq 4273 disp 1810028 proc 42143 real 42925
102 I: M19 T0 mirq 4273 disp 2369217 proc 42471 real 42925
103 I: M20 T0 mirq 4273 disp 2940429 proc 30427 real 30775
104 I: M21 T0 mirq 4273 disp 3524151 proc 35871 real 36850
105 I: M22 T0 mirq 4273 disp 4042148 proc 33738 real 34420
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/Zephyr-latest/arch/mips/core/
Dreset.S34 la t0, z_interrupt_stacks
36 add t1, t1, t0
41 sw t2, 0(t0)
42 addi t0, t0, 4
43 blt t0, t1, aa_loop
Disr.S43 op t0, ESF_O(t0)(sp) ;\
90 mfhi t0
92 OP_STOREREG t0, ESF_O(hi)(sp)
94 mfc0 t0, CP0_EPC
95 OP_STOREREG t0, ESF_O(epc)(sp)
98 mfc0 t0, CP0_STATUS
99 OP_STOREREG t0, ESF_O(status)(sp)
115 and t1, t1, t0
149 la t0, _offload_routine
150 OP_LOADREG t1, 0(t0)
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/Zephyr-latest/dts/bindings/watchdog/
Dnuvoton,npcx-watchdog.yaml13 t0-out:
17 Mapping table between Wake-Up Input (WUI) and t0-out timer expired signal.
18 For example, the WUI mapping on NPCX7 t0-out timer would be
19 t0-out = <&wui_t0out>;
/Zephyr-latest/drivers/interrupt_controller/
Dintc_nuclei_eclic.S53 csrr t0, 0x307 /* mtvt */
54 sub a0, a0, t0
55 la t0, _sw_isr_table
57 add t0, t0, a0
60 lw a0, 0(t0)
63 lw t1, RV_REGSIZE(t0)
/Zephyr-latest/soc/neorv32/
Dsoc_irq.S22 sll t0, t1, a0
23 csrrc t2, mie, t0
24 and t1, t2, t0
/Zephyr-latest/dts/bindings/led_strip/
Dworldsemi,ws2812-rpi_pico-pio.yaml17 The T0 is equal to T0H in the datasheet.
24 | T0 | T1+T2 |
31 | T0+T1 | T2 |
37 The T0～T2 means ratio in one period.
39 For example, T0=3, T1=3, T2=4 and the frequency is 800kHz case,
/Zephyr-latest/tests/kernel/tickless/tickless_concept/src/
Dmain.c71 volatile uint32_t t0, t1; in ZTEST() local
74 t0 = k_uptime_get_32(); in ZTEST()
77 TC_PRINT("time %d, %d\n", t0, t1); in ZTEST()
79 zassert_true((t1 - t0) >= SLEEP_TICKLESS); in ZTEST()
82 t0 = k_uptime_get_32(); in ZTEST()
85 TC_PRINT("time %d, %d\n", t0, t1); in ZTEST()
87 zassert_true((t1 - t0) >= SLEEP_TICKFUL); in ZTEST()
/Zephyr-latest/drivers/watchdog/
Dwdt_npcx.c14 * clocks and interrupts (T0 Timer) used for its callback functions in the
19 * LFCLK --->| T0 Prescale Counter |-+->| 16-Bit T0 Timer |--------> T0 Timer
73 /* t0 timer wake-up input source configuration */
100 /* Reload and restart T0 timer */ in wdt_t0out_reload()
109 LOG_ERR("Timeout: reload T0 timer!"); in wdt_t0out_reload()
163 * Configure the T0 wake-up event triggered from a rising edge in wdt_config_t0out_interrupt()
219 /* Disable irq of t0-out expired event first */ in wdt_npcx_setup()
245 * One clock period of T0 timer is 32/32.768 KHz = 0.976 ms. in wdt_npcx_setup()
272 /* Reload and restart T0 timer */ in wdt_npcx_setup()
275 /* Configure t0 timer interrupt and its isr. */ in wdt_npcx_setup()
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/Zephyr-latest/tests/subsys/fs/littlefs/src/
Dtest_lfs_perf.c33 uint32_t t0; in write_read() local
87 t0 = k_uptime_get_32(); in write_read()
97 if (t1 == t0) { in write_read()
116 tag, nbuf, buf_size, total, (t1 - t0), in write_read()
117 (uint32_t)(total * 1000U / (t1 - t0)), in write_read()
118 (uint32_t)(total * 1000U / (t1 - t0) / 1024U)); in write_read()
126 t0 = k_uptime_get_32(); in write_read()
136 if (t1 == t0) { in write_read()
142 tag, nbuf, buf_size, total, (t1 - t0), in write_read()
143 (uint32_t)(total * 1000U / (t1 - t0)), in write_read()
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