Lines Matching full:t0
21 la t0, _ITB_BASE_
22 csrw NDS_UITB, t0
27 li t0, (1 << 9) | (1 << 0)
28 csrs NDS_MCACHE_CTL, t0
36 li t0, (0x3 << 13)
37 csrc NDS_MCACHE_CTL, t0
38 li t0, (1 << 19) | (1 << 13) | (1 << 10) | (1 << 1)
39 csrs NDS_MCACHE_CTL, t0
42 csrr t0, NDS_MCACHE_CTL
44 and t0, t0, t1
45 beqz t0, cache_enable_finish
50 csrr t0, NDS_MCACHE_CTL
51 and t0, t0, t1
52 beqz t0, check_cm_enabled
58 li t0, (1 << 8) | (1 << 6)
59 csrs NDS_MMISC_CTL, t0