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/Zephyr-latest/soc/st/stm32/stm32l0x/
DKconfig.defconfig1 # ST Microelectronics STM32L0 MCU line
6 # Kconfig symbols common to STM32L0 series
10 rsource "Kconfig.defconfig.stm32l0*"
Dsoc.c9 * @brief System/hardware module for STM32L0 processor
35 /* On STM32L0, there are some hardfault when enabling DBGMCU bit: in soc_early_init_hook()
DKconfig1 # ST Microelectronics STM32L0 MCU series
Dsoc.h8 * @file SoC configuration macros for the STM32L0 family processors.
DKconfig.soc1 # ST Microelectronics STM32L0 MCU line
/Zephyr-latest/dts/arm/st/l0/
Dstm32l010.dtsi7 #include <st/l0/stm32l0.dtsi>
11 compatible = "st,stm32l010", "st,stm32l0", "simple-bus";
Dstm32l031.dtsi7 #include <st/l0/stm32l0.dtsi>
11 compatible = "st,stm32l031", "st,stm32l0", "simple-bus";
Dstm32l073.dtsi12 compatible = "st,stm32l073", "st,stm32l0", "simple-bus";
Dstm32l081.dtsi11 compatible = "st,stm32l081", "st,stm32l0", "simple-bus";
Dstm32l051.dtsi7 #include <st/l0/stm32l0.dtsi>
11 compatible = "st,stm32l051", "st,stm32l0", "simple-bus";
Dstm32l053.dtsi21 compatible = "st,stm32l053", "st,stm32l0", "simple-bus";
Dstm32l072.dtsi24 compatible = "st,stm32l072", "st,stm32l0", "simple-bus";
Dstm32l071.dtsi7 #include <st/l0/stm32l0.dtsi>
11 compatible = "st,stm32l071", "st,stm32l0", "simple-bus";
Dstm32l0.dtsi66 compatible = "st,stm32l0-msi-clock";
88 compatible = "st,stm32l0-pll-clock";
120 compatible = "st,stm32l0-nv-flash", "st,stm32-nv-flash",
/Zephyr-latest/dts/bindings/mtd/
Dst,stm32l0-nv-flash.yaml2 ST STM32L0 family flash memory.
6 compatible: st,stm32l0-nv-flash
/Zephyr-latest/dts/bindings/clock/
Dst,stm32l0-msi-clock.yaml4 description: STM32L0 and STM32L1 Multi Speed Internal Clock
6 compatible: "st,stm32l0-msi-clock"
Dst,stm32l0-pll-clock.yaml5 STM32L0 and STM32L1 Main PLL node binding:
18 compatible: "st,stm32l0-pll-clock"
/Zephyr-latest/boards/st/nucleo_l011k4/support/
Dopenocd.cfg9 source [find target/stm32l0.cfg]
/Zephyr-latest/boards/st/nucleo_l031k6/support/
Dopenocd.cfg7 source [find target/stm32l0.cfg]
/Zephyr-latest/boards/st/nucleo_l053r8/support/
Dopenocd.cfg9 source [find target/stm32l0.cfg]
/Zephyr-latest/boards/st/nucleo_l073rz/support/
Dopenocd.cfg9 source [find target/stm32l0.cfg]
/Zephyr-latest/drivers/interrupt_controller/
Dintc_exti_stm32.c23 #include <zephyr/dt-bindings/pinctrl/stm32-pinctrl-common.h> /* For STM32L0 series */
354 * Ports F and G are not present on some STM32L0 parts, so in stm32_exti_set_line_src_port()
395 * Ports F and G are not present on some STM32L0 parts, so in stm32_exti_get_line_src_port()
/Zephyr-latest/scripts/build/
Duf2families.json29 "short_name": "STM32L0",
/Zephyr-latest/dts/arm/st/l1/
Dstm32l1.dtsi57 compatible = "st,stm32l0-msi-clock";
78 compatible = "st,stm32l0-pll-clock";
/Zephyr-latest/boards/dragino/lsn50/doc/
Dindex.rst10 STM32L0 Series features.

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