1 /* 2 * Copyright (c) 2018 Endre Karlson <endre.karlson@gmail.com> 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7 /** 8 * @file 9 * @brief System/hardware module for STM32L0 processor 10 */ 11 12 #include <zephyr/device.h> 13 #include <zephyr/init.h> 14 #include <zephyr/linker/linker-defs.h> 15 #include <string.h> 16 #include <stm32_ll_bus.h> 17 #include <stm32_ll_system.h> 18 19 #include <cmsis_core.h> 20 21 /** 22 * @brief Perform basic hardware initialization at boot. 23 * 24 * This needs to be run from the very beginning. 25 */ soc_early_init_hook(void)26void soc_early_init_hook(void) 27 { 28 /* Enable ART accelerator prefetch */ 29 LL_FLASH_EnablePrefetch(); 30 31 /* Update CMSIS SystemCoreClock variable (HCLK) */ 32 /* At reset, system core clock is set to 2.1 MHz from MSI */ 33 SystemCoreClock = 2097152; 34 35 /* On STM32L0, there are some hardfault when enabling DBGMCU bit: 36 * Sleep, Stop or Standby. 37 * See https://github.com/zephyrproject-rtos/zephyr/issues/#37119 38 * For unclear reason, enabling DMA clock fixes this issue 39 * (similarly than it fixes 40 * https://github.com/zephyrproject-rtos/zephyr/issues/#34324 ) 41 */ 42 LL_AHB1_GRP1_EnableClock(LL_AHB1_GRP1_PERIPH_DMA1); 43 #ifdef CONFIG_PM 44 /* Enable Power clock */ 45 LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_PWR); 46 #endif 47 } 48
