Searched full:pa0 (Results 1 – 25 of 29) sorted by relevance
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| /hal_gigadevice-latest/pinconfigs/ |
| D | README.md | 5 to `PA0` and `PC8`. These configurations can be used to generate valid pin
102 # Configuration for pin 'PA0'. Supported on V, R, C, T pincodes, valid
104 PA0:
148 # Configuration for pin 'PA0'. Available on pin codes I, Z, V and has
150 PA0:
175 | USART0_CTS | PA0 |
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| D | gd32vf103xx.yml | 384 PA0:
679 pins: [PA0, PA15, PA0, PA15]
687 pins: [PA0, PA15, PA0, PA15]
711 pins: [PA0, PD3]
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| D | gd32e103xx.yml | 451 PA0:
742 pins: [PA0, PA15, PA0, PA15]
750 pins: [PA0, PA15, PA0, PA15]
774 pins: [PA0, PD3]
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| D | gd32e507xx.yml | 702 PA0:
1115 pins: [PA0, PA15, PA0, PA15]
1123 pins: [PA0, PA15, PA0, PA15]
1159 pins: [PA0, PD3]
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| D | gd32f403xx.yml | 485 PA0:
912 pins: [PA0, PD3]
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| D | gd32f350xx.yml | 89 PA0:
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| D | gd32a503xx.yml | 37 PA0:
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| D | gd32l233xx.yml | 146 PA0:
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| D | gd32f405xx.yml | 34 PA0:
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| /hal_gigadevice-latest/scripts/tests/gd32pinctrl/data/ |
| D | gd32f999xx.yml | 38 PA0:
59 pins: [PA0, PA1]
61 pins: [PA1, PA0]
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| D | gd32f888xx.yml | 28 PA0:
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| /hal_gigadevice-latest/gd32a50x/standard_peripheral/include/ |
| D | gd32a50x_cmp.h | 80 CMP_IM_PA0 = 43, /*!< PA0 */
92 CMP_IP_PA0, /*!< PA0 */
151 …0 CS_CMPMSEL(43) /*!< CMP inverting external input PA0 */
162 … CS_CMPPSEL_PA0 CS_CMPPSEL(3) /*!< CMP plus input PA0 */
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| D | gd32a50x_pmu.h | 98 #define PMU_WAKEUP_PIN0 PMU_CS_WUPEN0 /*!< WKUP Pin 0 (PA0) enable */
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| /hal_gigadevice-latest/gd32a50x/standard_peripheral/source/ |
| D | gd32a50x_cmp.c | 64 \arg CMP_IM_PA0: CMP inverting input PA0
73 \arg CMP_IP_PA0: CMP plus input PA0
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| D | gd32a50x_pmu.c | 286 \arg PMU_WAKEUP_PIN0: WKUP Pin 0 (PA0)
300 \arg PMU_WAKEUP_PIN0: WKUP Pin 0 (PA0)
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| /hal_gigadevice-latest/gd32f3x0/standard_peripheral/source/ |
| D | gd32f3x0_pmu.c | 314 \arg PMU_WAKEUP_PIN0: WKUP Pin 0 (PA0)
331 \arg PMU_WAKEUP_PIN0: WKUP Pin 0 (PA0)
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| D | gd32f3x0_cmp.c | 67 \arg CMP_PA_0_2: PA0 or PA2 input
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| /hal_gigadevice-latest/gd32f3x0/standard_peripheral/include/ |
| D | gd32f3x0_cmp.h | 87 …CMP_PA_0_2 /*!< PA0 or PA2 input …
127 …MP0MSEL_PA0 CS_CMP0MSEL(6) /*!< CMP0 inverting input PA0*/
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| D | gd32f3x0_pmu.h | 133 #define PMU_WAKEUP_PIN0 PMU_CS_WUPEN0 /*!< WKUP Pin 0 (PA0) enable */
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| /hal_gigadevice-latest/gd32l23x/standard_peripheral/source/ |
| D | gd32l23x_pmu.c | 282 \arg PMU_WAKEUP_PIN0: WKUP Pin 0 (PA0)
299 \arg PMU_WAKEUP_PIN0: WKUP Pin 0 (PA0)
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| D | gd32l23x_cmp.c | 70 \arg CMP_PA0_PA2: PA0 input when selecting CMP0, PA2 input when selecting CMP1
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| /hal_gigadevice-latest/gd32e50x/standard_peripheral/source/ |
| D | gd32e50x_pmu.c | 403 \arg PMU_WAKEUP_PIN0: WKUP Pin 0 (PA0)
423 \arg PMU_WAKEUP_PIN0: WKUP Pin 0 (PA0)
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| /hal_gigadevice-latest/gd32l23x/standard_peripheral/include/ |
| D | gd32l23x_cmp.h | 91 …CMP_PA0_PA2, /*!< PA0 input when s…
159 …0MSEL_PA0 CS_CMP0MSEL(4) /*!< CMP0 inverting input PA0 */
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| /hal_gigadevice-latest/scripts/ |
| D | gd32pinctrl.py | 66 pin_name: Pin name, e.g. PA0
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| /hal_gigadevice-latest/gd32e50x/standard_peripheral/include/ |
| D | gd32e50x_pmu.h | 126 #define PMU_WAKEUP_PIN0 PMU_CS0_WUPEN0 /*!< WKUP Pin 0 (PA0) enable */
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