1 /*! 2 \file gd32l23x_cmp.h 3 \brief definitions for the CMP 4 5 \version 2021-08-04, V1.0.0, firmware for GD32L23x 6 */ 7 8 /* 9 Copyright (c) 2021, GigaDevice Semiconductor Inc. 10 11 Redistribution and use in source and binary forms, with or without modification, 12 are permitted provided that the following conditions are met: 13 14 1. Redistributions of source code must retain the above copyright notice, this 15 list of conditions and the following disclaimer. 16 2. Redistributions in binary form must reproduce the above copyright notice, 17 this list of conditions and the following disclaimer in the documentation 18 and/or other materials provided with the distribution. 19 3. Neither the name of the copyright holder nor the names of its contributors 20 may be used to endorse or promote products derived from this software without 21 specific prior written permission. 22 23 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 24 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 25 WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 26 IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 27 INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 28 NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 29 PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 30 WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 32 OF SUCH DAMAGE. 33 */ 34 35 #ifndef GD32L23X_CMP_H 36 #define GD32L23X_CMP_H 37 38 #include "gd32l23x.h" 39 40 /* CMP definitions */ 41 #define CMP0 CMP_BASE + 0x00000000U /*!< CMP0 base address */ 42 #define CMP1 CMP_BASE + 0x00000004U /*!< CMP1 base address */ 43 44 /* registers definitions */ 45 #define CMP0_CS REG32(CMP0 + 0x00000000U) /*!< CMP0 control and status register */ 46 #define CMP1_CS REG32(CMP1 + 0x00000000U) /*!< CMP1 control and status register */ 47 48 /* bits definitions */ 49 /* CMP0_CS */ 50 #define CMP0_CS_EN BIT(0) /*!< CMP0 enable */ 51 #define CMP0_CS_PM BITS(2,3) /*!< CMP0 mode */ 52 #define CMP0_CS_MSEL BITS(4,6) /*!< CMP0 minus input selection */ 53 #define CMP0_CS_OSEL BITS(13,14) /*!< CMP0 output selection */ 54 #define CMP0_CS_PL BIT(15) /*!< CMP0 output polarity */ 55 #define CMP0_CS_HST BITS(16,17) /*!< CMP0 hysteresis */ 56 #define CMP0_CS_BLK BITS(18,20) /*!< CMP0 blanking source selection */ 57 #define CMP0_CS_BEN BIT(22) /*!< CMP0 scaler bridge enable bit */ 58 #define CMP0_CS_SEN BIT(23) /*!< CMP0 voltage input scaler */ 59 #define CMP0_CS_OUT BIT(30) /*!< CMP0 output state bit */ 60 #define CMP0_CS_LK BIT(31) /*!< CMP0 lock */ 61 62 /* CMP1_CS */ 63 #define CMP1_CS_EN BIT(0) /*!< CMP1 enable */ 64 #define CMP1_CS_WEN BIT(1) /*!< CMP window mode enable */ 65 #define CMP1_CS_PM BITS(2,3) /*!< CMP1 mode */ 66 #define CMP1_CS_MSEL BITS(4,6) /*!< CMP1 minus input selection */ 67 #define CMP1_CS_PSEL BITS(8,10) /*!< CMP1 plus input selection */ 68 #define CMP1_CS_OSEL BITS(13,14) /*!< CMP1 output selection */ 69 #define CMP1_CS_PL BIT(15) /*!< CMP1 output polarity */ 70 #define CMP1_CS_HST BITS(16,17) /*!< CMP1 hysteresis */ 71 #define CMP1_CS_BLK BITS(18,20) /*!< CMP1 blanking source selection */ 72 #define CMP1_CS_BEN BIT(22) /*!< CMP1 scaler bridge enable bit */ 73 #define CMP1_CS_SEN BIT(23) /*!< CMP1 voltage input scaler */ 74 #define CMP1_CS_OUT BIT(30) /*!< CMP1 output state bit */ 75 #define CMP1_CS_LK BIT(31) /*!< CMP1 lock */ 76 77 /* constants definitions */ 78 /* operating mode */ 79 typedef enum { 80 CMP_HIGHSPEED = 0, /*!< high speed mode */ 81 CMP_MIDDLESPEED, /*!< medium speed mode */ 82 CMP_LOWSPEED /*!< low speed mode */ 83 } operating_mode_enum; 84 85 /* inverting input */ 86 typedef enum { 87 CMP_1_4VREFINT = 0, /*!< VREFINT /4 input */ 88 CMP_1_2VREFINT, /*!< VREFINT /2 input */ 89 CMP_3_4VREFINT, /*!< VREFINT *3/4 input */ 90 CMP_VREFINT, /*!< VREFINT input */ 91 CMP_PA0_PA2, /*!< PA0 input when selecting CMP0, PA2 input when selecting CMP1 */ 92 CMP_DACOUT_PA4, /*!< DAC_OUT0(PA4) input */ 93 CMP_PB3 /*!< PB3 input only for CMP1 */ 94 } inverting_input_enum; 95 96 /* plus input */ 97 typedef enum { 98 CMP1_PA3 = 0, /*!< PA3 */ 99 CMP1_PB4, /*!< PB4 */ 100 CMP1_PB5, /*!< PB5 */ 101 CMP1_PB6, /*!< PB6 */ 102 CMP1_PB7 /*!< PB7 */ 103 } CMP1_plus_input_enum; 104 105 /* hysteresis */ 106 typedef enum { 107 CMP_HYSTERESIS_NO = 0, /*!< output no hysteresis */ 108 CMP_HYSTERESIS_LOW, /*!< output low hysteresis */ 109 CMP_HYSTERESIS_MIDDLE, /*!< output middle hysteresis */ 110 CMP_HYSTERESIS_HIGH /*!< output high hysteresis */ 111 } cmp_hysteresis_enum; 112 113 /* output */ 114 typedef enum { 115 CMP_OUTPUT_NONE = 0, /*!< output no selection */ 116 CMP_OUTPUT_TIMER1IC3, /*!< TIMER 1 channel3 input capture */ 117 CMP_OUTPUT_TIMER2IC0, /*!< TIMER 2 channel0 input capture */ 118 CMP_OUTPUT_LPTIMERIC0_IC1 /*!< LPTIMER channel0 or channel1 input capture */ 119 } cmp_output_enum; 120 121 /* output inv */ 122 typedef enum { 123 CMP_OUTPUT_POLARITY_INVERTED = 0, /*!< output is inverted */ 124 CMP_OUTPUT_POLARITY_NOINVERTED /*!< output is not inverted */ 125 } cmp_output_inv_enum; 126 127 /* blanking_sourc */ 128 typedef enum { 129 CMP_BLANKING_NONE = 0, /*!< output no selection */ 130 CMP_BLANKING_TIMER1_OC1 = 1, /*!< TIMER 1 output channel 1 */ 131 CMP_BLANKING_TIMER2_OC1 = 2, /*!< TIMER 2 output channel 1 */ 132 CMP_BLANKING_TIMER8_OC1 = 4, /*!< TIMER 8 output channel 1 */ 133 CMP_BLANKING_TIMER11_OC1 = 5 /*!< TIMER 11 output channel 1 */ 134 } blanking_source_enum; 135 136 /* output state */ 137 typedef enum { 138 CMP_OUTPUTLEVEL_LOW = 0, /*!< the output is low */ 139 CMP_OUTPUTLEVEL_HIGH /*!< the output is high */ 140 } cmp_output_state_enum; 141 142 /* CMP0 enable bit*/ 143 #define CS_CMP0EN(regval) (BIT(0) & ((uint32_t)(regval) << 0)) 144 #define CS_CMP0EN_DISABLE CS_CMP0EN(0) /*!< CMP0 enable */ 145 #define CS_CMP0EN_ENABLE CS_CMP0EN(1) /*!< CMP0 disable */ 146 147 /* CMP0 mode */ 148 #define CS_CMP0PM(regval) (BITS(2,3) & ((uint32_t)(regval) << 2)) 149 #define CS_CMP0PM_HIGHSPEED CS_CMP0PM(0) /*!< CMP0 mode high speed */ 150 #define CS_CMP0PM_MEDIUMSPEED CS_CMP0PM(1) /*!< CMP0 mode medium speed */ 151 #define CS_CMP0PM_LOWSPEED CS_CMP0PM(3) /*!< CMP0 mode low speed */ 152 153 /* CMP0 inverting input */ 154 #define CS_CMP0MSEL(regval) (BITS(4,6) & ((uint32_t)(regval) << 4)) 155 #define CS_CMP0MSEL_1_4VREFINT CS_CMP0MSEL(0) /*!< CMP0 inverting input 1/4 Vrefint */ 156 #define CS_CMP0MSEL_1_2VREFINT CS_CMP0MSEL(1) /*!< CMP0 inverting input 1/2 Vrefint */ 157 #define CS_CMP0MSEL_3_4VREFINT CS_CMP0MSEL(2) /*!< CMP0 inverting input 3/4 Vrefint */ 158 #define CS_CMP0MSEL_VREFINT CS_CMP0MSEL(3) /*!< CMP0 inverting input Vrefint */ 159 #define CS_CMP0MSEL_PA0 CS_CMP0MSEL(4) /*!< CMP0 inverting input PA0 */ 160 #define CS_CMP0MSEL_DAC_OUT CS_CMP0MSEL(5) /*!< CMP0 inverting input DAC_OUT/PA4 */ 161 162 /* CMP0 output selection */ 163 #define CS_CMP0OSEL(regval) (BITS(13,14) & ((uint32_t)(regval) << 13)) 164 #define CS_CMP0OSEL_NOSELECTION CS_CMP0OSEL(0) /*!< CMP0 no output selection */ 165 #define CS_CMP0OSEL_TIMER1CI3 CS_CMP0OSEL(1) /*!< CMP0 as TIMER1 channel 3 input capture source */ 166 #define CS_CMP0OSEL_TIMER2CI0 CS_CMP0OSEL(2) /*!< CMP0 as TIMER2 channel 0 input capture source */ 167 #define CS_CMP0OSEL_LPTIMERCI0 CS_CMP0OSEL(3) /*!< CMP0 as LPTIMER channel 0 input capture source */ 168 169 /* CMP0 output polarity*/ 170 #define CS_CMP0PL(regval) (BIT(15) & ((uint32_t)(regval) << 15)) 171 #define CS_CMP0PL_NOL CS_CMP0PL(0) /*!< CMP0 output not inverted */ 172 #define CS_CMP0PL_INV CS_CMP0PL(1) /*!< CMP0 output inverted */ 173 174 /* CMP0 hysteresis */ 175 #define CS_CMP0HST(regval) (BITS(16,17) & ((uint32_t)(regval) << 16)) 176 #define CS_CMP0HST_HYSTERESIS_NO CS_CMP0HST(0) /*!< CMP0 output no hysteresis */ 177 #define CS_CMP0HST_HYSTERESIS_LOW CS_CMP0HST(1) /*!< CMP0 output low hysteresis */ 178 #define CS_CMP0HST_HYSTERESIS_MEDIUM CS_CMP0HST(2) /*!< CMP0 output medium hysteresis */ 179 #define CS_CMP0HST_HYSTERESIS_HIGH CS_CMP0HST(3) /*!< CMP0 output high hysteresis */ 180 181 /* CMP0 Blanking suorce */ 182 #define CS_CMP0BLK(regval) (BITS(18,20) & ((uint32_t)(regval) << 18)) 183 #define CS_CMP0BLK_NOBLK CS_CMP0BLK(0) /*!< CMP0 no blanking */ 184 #define CS_CMP0BLK_TIMER1_OC1 CS_CMP0BLK(1) /*!< CMP0 TIMER1 OC1 selected as blanking source */ 185 #define CS_CMP0BLK_TIMER2_OC1 CS_CMP0BLK(2) /*!< CMP0 TIMER2 OC1 selected as blanking source */ 186 #define CS_CMP0BLK_TIMER8_OC1 CS_CMP0BLK(4) /*!< CMP0 TIMER8 OC1 selected as blanking source */ 187 #define CS_CMP0BLK_TIMER11_OC1 CS_CMP0BLK(5) /*!< CMP0 TIMER11 OC1 selected as blanking source */ 188 189 /* CMP0 bridge enable*/ 190 #define CS_CMP0BEN(regval) (BIT(22) & ((uint32_t)(regval) << 22)) 191 #define CS_CMP0BEN_DISABLE CS_CMP0BEN(0) /*!< CMP0 scaler bridge enable */ 192 #define CS_CMP0BEN_ENABLE CS_CMP0BEN(1) /*!< CMP0 scaler bridge disable */ 193 194 /* CMP0 voltage scaler*/ 195 #define CS_CMP0SEN(regval) (BIT(23) & ((uint32_t)(regval) << 23)) 196 #define CS_CMP0SEN_DISABLE CS_CMP0SEN(0) /*!< CMP0 voltage scaler enable */ 197 #define CS_CMP0SEN_ENABLE CS_CMP0SEN(1) /*!< CMP0 voltage scaler disable */ 198 199 /* CMP0 output state bit*/ 200 #define CS_CMP0OUT(regval) (BIT(30) & ((uint32_t)(regval) << 30)) 201 #define CS_CMP0OUT_DISABLE CS_CMP0LK(0) /*!< Non-inverting input below inverting input and the output is low */ 202 #define CS_CMP0OUT_ENABLE CS_CMP0LK(1) /*!< Non-inverting input above inverting input and the output is high */ 203 204 /* CMP0 lock bit*/ 205 #define CS_CMP0LK(regval) (BIT(31) & ((uint32_t)(regval) << 31)) 206 #define CS_CMP0LK_DISABLE CS_CMP0LK(0) /*!< CMP0 voltage scaler enable */ 207 #define CS_CMP0LK_ENABLE CS_CMP0LK(1) /*!< CMP0 voltage scaler disable */ 208 209 /* CMP1 enable bit*/ 210 #define CS_CMP1EN(regval) (BIT(0) & ((uint32_t)(regval) << 0)) 211 #define CS_CMP1EN_DISABLE CS_CMP1EN(0) /*!< CMP1 enable */ 212 #define CS_CMP1EN_ENABLE CS_CMP1EN(1) /*!< CMP1 disable */ 213 214 /* CMP1 window mode*/ 215 #define CS_CMP1WEN(regval) (BIT(1) & ((uint32_t)(regval) << 1)) 216 #define CS_CMP1WEN_DISABLE CS_CMP1WEN(0) /*!< Input plus of CMP1 is not connected to CMP0 */ 217 #define CS_CMP1WEN_ENABLE CS_CMP1WEN(1) /*!< Input plus of CMP1 is connected with input plus of CMP0 */ 218 219 /* CMP1 mode */ 220 #define CS_CMP1PM(regval) (BITS(2,3) & ((uint32_t)(regval) << 2)) 221 #define CS_CMP1PM_HIGHSPEED CS_CMP1PM(0) /*!< CMP1 mode high speed */ 222 #define CS_CMP1PM_MEDIUMSPEED CS_CMP1PM(1) /*!< CMP1 mode medium speed */ 223 #define CS_CMP1PM_LOWSPEED CS_CMP1PM(3) /*!< CMP1 mode low speed */ 224 225 /* CMP1 minus input */ 226 #define CS_CMP1MSEL(regval) (BITS(4,6) & ((uint32_t)(regval) << 4)) 227 #define CS_CMP1MSEL_1_4VREFINT CS_CMP1MSEL(0) /*!< CMP1 inverting input 1/4 Vrefint */ 228 #define CS_CMP1MSEL_1_2VREFINT CS_CMP1MSEL(1) /*!< CMP1 inverting input 1/2 Vrefint */ 229 #define CS_CMP1MSEL_3_4VREFINT CS_CMP1MSEL(2) /*!< CMP1 inverting input 3/4 Vrefint */ 230 #define CS_CMP1MSEL_VREFINT CS_CMP1MSEL(3) /*!< CMP1 inverting input Vrefint */ 231 #define CS_CMP1MSEL_PA2 CS_CMP1MSEL(4) /*!< CMP1 inverting input PA2 */ 232 #define CS_CMP1MSEL_DAC_OUT CS_CMP1MSEL(5) /*!< CMP1 inverting input DAC_OUT/PA4 */ 233 #define CS_CMP1MSEL_PB3 CS_CMP1MSEL(6) /*!< CMP1 inverting input PB3*/ 234 235 /* CMP1 plus input*/ 236 #define CS_CMP1PSEL(regval) (BITS(8,10) & ((uint32_t)(regval) << 8)) 237 #define CS_CMP1PSEL_PA3 CS_CMP1PSEL(0) /*!< CMP1 plus input PA3 */ 238 #define CS_CMP1PSEL_PB4 CS_CMP1PSEL(1) /*!< CMP1 plus input PB4 */ 239 #define CS_CMP1PSEL_PB5 CS_CMP1PSEL(2) /*!< CMP1 plus input PB5 */ 240 #define CS_CMP1PSEL_PB6 CS_CMP1PSEL(3) /*!< CMP1 plus input PB6 */ 241 #define CS_CMP1PSEL_PB7 CS_CMP1PSEL(4) /*!< CMP1 plus input PB7 */ 242 243 /* CMP1 output selection */ 244 #define CS_CMP1OSEL(regval) (BITS(13,14) & ((uint32_t)(regval) << 13)) 245 #define CS_CMP1OSEL_NOSELECTION CS_CMP1OSEL(0) /*!< CMP1 no output selection */ 246 #define CS_CMP1OSEL_TIMER1CI3 CS_CMP1OSEL(1) /*!< CMP1 as TIMER1 channel 3 input capture source */ 247 #define CS_CMP1OSEL_TIMER2CI0 CS_CMP1OSEL(2) /*!< CMP1 as TIMER2 channel 0 input capture source */ 248 #define CS_CMP1OSEL_LPTIMERCI1 CS_CMP1OSEL(3) /*!< CMP1 as LPTIMER channel 1 input capture source */ 249 250 /* CMP1 output polarity*/ 251 #define CS_CMP1PL(regval) (BIT(15) & ((uint32_t)(regval) << 15)) 252 #define CS_CMP1PL_NOL CS_CMP1PL(0) /*!< CMP1 output not inverted */ 253 #define CS_CMP1PL_INV CS_CMP1PL(1) /*!< CMP1 output inverted */ 254 255 /* CMP1 hysteresis */ 256 #define CS_CMP1HST(regval) (BITS(16,17) & ((uint32_t)(regval) << 16)) 257 #define CS_CMP1HST_HYSTERESIS_NO CS_CMP1HST(0) /*!< CMP1 output no hysteresis */ 258 #define CS_CMP1HST_HYSTERESIS_LOW CS_CMP1HST(1) /*!< CMP1 output low hysteresis */ 259 #define CS_CMP1HST_HYSTERESIS_MEDIUM CS_CMP1HST(2) /*!< CMP1 output medium hysteresis */ 260 #define CS_CMP1HST_HYSTERESIS_HIGH CS_CMP1HST(3) /*!< CMP1 output high hysteresis */ 261 262 /* CMP1 Blanking suorce */ 263 #define CS_CMP1BLK(regval) (BITS(18,20) & ((uint32_t)(regval) << 18)) 264 #define CS_CMP1BLK_NOBLK CS_CMP1BLK(0) /*!< CMP1 no blanking */ 265 #define CS_CMP1BLK_TIMER1_OC1 CS_CMP1BLK(1) /*!< CMP1 TIMER1 OC1 selected as blanking source */ 266 #define CS_CMP1BLK_TIMER2_OC1 CS_CMP1BLK(2) /*!< CMP1 TIMER2 OC1 selected as blanking source */ 267 #define CS_CMP1BLK_TIMER8_OC1 CS_CMP1BLK(4) /*!< CMP1 TIMER8 OC1 selected as blanking source */ 268 #define CS_CMP1BLK_TIMER11_OC1 CS_CMP1BLK(5) /*!< CMP1 TIMER11 OC1 selected as blanking source */ 269 270 /* CMP1 bridge enable*/ 271 #define CS_CMP1BEN(regval) (BIT(22) & ((uint32_t)(regval) << 22)) 272 #define CS_CMP1BEN_DISABLE CS_CMP1BEN(0) /*!< CMP1 scaler bridge enable */ 273 #define CS_CMP1BEN_ENABLE CS_CMP1BEN(1) /*!< CMP1 scaler bridge disable */ 274 275 /* CMP1 voltage scaler*/ 276 #define CS_CMP1SEN(regval) (BIT(23) & ((uint32_t)(regval) << 23)) 277 #define CS_CMP1SEN_DISABLE CS_CMP1SEN(0) /*!< CMP1 voltage scaler enable */ 278 #define CS_CMP1SEN_ENABLE CS_CMP1SEN(1) /*!< CMP1 voltage scaler disable */ 279 280 /* CMP1 output state bit*/ 281 #define CS_CMP1OUT(regval) (BIT(30) & ((uint32_t)(regval) << 30)) 282 #define CS_CMP1OUT_DISABLE CS_CMP1LK(0) /*!< Non-inverting input below inverting input and the output is low */ 283 #define CS_CMP1OUT_ENABLE CS_CMP1LK(1) /*!< Non-inverting input above inverting input and the output is high */ 284 285 /* CMP1 lock bit*/ 286 #define CS_CMP1LK(regval) (BIT(31) & ((uint32_t)(regval) << 31)) 287 #define CS_CMP1LK_DISABLE CS_CMP1LK(0) /*!< CMP1 voltage scaler enable */ 288 #define CS_CMP1LK_ENABLE CS_CMP1LK(1) /*!< CMP1 voltage scaler disable */ 289 290 /* function declarations */ 291 /* initialization functions */ 292 /* deinitialize comparator */ 293 void cmp_deinit(uint32_t cmp_periph); 294 /* initialize comparator mode */ 295 void cmp_mode_init(uint32_t cmp_periph, operating_mode_enum operating_mode, inverting_input_enum inverting_input, cmp_hysteresis_enum output_hysteresis); 296 /* selecte the plus input for CMP1 */ 297 void cmp1_plus_selection(CMP1_plus_input_enum plus_input); 298 /* initialize comparator output */ 299 void cmp_output_init(uint32_t cmp_periph, cmp_output_enum output_selection, cmp_output_inv_enum output_polarity); 300 /* initialize comparator blanking function */ 301 void cmp_blanking_init(uint32_t cmp_periph, blanking_source_enum blanking_source_selection); 302 303 304 /* enable functions */ 305 /* enable comparator */ 306 void cmp_enable(uint32_t cmp_periph); 307 /* disable comparator */ 308 void cmp_disable(uint32_t cmp_periph); 309 /* enable the window mode */ 310 void cmp_window_enable(void); 311 /* disable the window mode */ 312 void cmp_window_disable(void); 313 /* enable the voltage scaler */ 314 void cmp_voltage_scaler_enable(uint32_t cmp_periph); 315 /* disable the voltage scaler */ 316 void cmp_voltage_scaler_disable(uint32_t cmp_periph); 317 /* enable the scaler bridge */ 318 void cmp_scaler_bridge_enable(uint32_t cmp_periph); 319 /* disable the scaler bridge */ 320 void cmp_scaler_bridge_disable(uint32_t cmp_periph); 321 /* lock the comparator */ 322 void cmp_lock_enable(uint32_t cmp_periph); 323 324 /* output functions */ 325 /* get output level */ 326 uint32_t cmp_output_level_get(uint32_t cmp_periph); 327 328 #endif /* GD32L23X_CMP_H */ 329
