1 /*! 2 \file gd32e50x_pmu.h 3 \brief definitions for the PMU 4 5 \version 2020-03-10, V1.0.0, firmware for GD32E50x 6 \version 2020-08-26, V1.1.0, firmware for GD32E50x 7 \version 2021-03-23, V1.2.0, firmware for GD32E50x 8 */ 9 10 /* 11 Copyright (c) 2021, GigaDevice Semiconductor Inc. 12 13 Redistribution and use in source and binary forms, with or without modification, 14 are permitted provided that the following conditions are met: 15 16 1. Redistributions of source code must retain the above copyright notice, this 17 list of conditions and the following disclaimer. 18 2. Redistributions in binary form must reproduce the above copyright notice, 19 this list of conditions and the following disclaimer in the documentation 20 and/or other materials provided with the distribution. 21 3. Neither the name of the copyright holder nor the names of its contributors 22 may be used to endorse or promote products derived from this software without 23 specific prior written permission. 24 25 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 26 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 27 WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 28 IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 29 INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 30 NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 31 PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 32 WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 34 OF SUCH DAMAGE. 35 */ 36 37 #ifndef GD32E50X_PMU_H 38 #define GD32E50X_PMU_H 39 40 #include "gd32e50x.h" 41 42 /* PMU definitions */ 43 #define PMU PMU_BASE /*!< PMU base address */ 44 45 /* registers definitions */ 46 #define PMU_CTL0 REG32((PMU) + 0x00000000U) /*!< PMU control register 0 */ 47 #define PMU_CS0 REG32((PMU) + 0x00000004U) /*!< PMU control and status register 0 */ 48 #define PMU_CTL1 REG32((PMU) + 0x00000008U) /*!< PMU control register 1 */ 49 #define PMU_CS1 REG32((PMU) + 0x0000000CU) /*!< PMU control and status register 1 */ 50 51 /* bits definitions */ 52 /* PMU_CTL0 */ 53 #define PMU_CTL0_LDOLP BIT(0) /*!< LDO low power mode */ 54 #define PMU_CTL0_STBMOD BIT(1) /*!< standby mode */ 55 #define PMU_CTL0_WURST BIT(2) /*!< wakeup flag reset */ 56 #define PMU_CTL0_STBRST BIT(3) /*!< standby flag reset */ 57 #define PMU_CTL0_LVDEN BIT(4) /*!< low voltage detector enable */ 58 #define PMU_CTL0_LVDT BITS(5,7) /*!< low voltage detector threshold */ 59 #define PMU_CTL0_BKPWEN BIT(8) /*!< backup domain write enable */ 60 #define PMU_CTL0_LDLP BIT(10) /*!< low-driver mode when use low power LDO */ 61 #define PMU_CTL0_LDNP BIT(11) /*!< low-driver mode when use normal power LDO */ 62 #define PMU_CTL0_HDEN BIT(16) /*!< high-driver mode enable */ 63 #define PMU_CTL0_HDS BIT(17) /*!< high-driver mode switch */ 64 #define PMU_CTL0_LDEN BITS(18,19) /*!< low-driver mode enable in deep-sleep/deep-sleep 1/deep-sleep 2 mode */ 65 66 /* PMU_CS0 */ 67 #define PMU_CS0_WUF BIT(0) /*!< wakeup flag */ 68 #define PMU_CS0_STBF BIT(1) /*!< standby flag */ 69 #define PMU_CS0_LVDF BIT(2) /*!< low voltage detector status flag */ 70 #define PMU_CS0_WUPEN6 BIT(7) /*!< wakeup pin 6 enable */ 71 #define PMU_CS0_WUPEN0 BIT(8) /*!< wakeup pin 0 enable */ 72 #define PMU_CS0_WUPEN1 BIT(9) /*!< wakeup pin 1 enable */ 73 #define PMU_CS0_WUPEN2 BIT(10) /*!< wakeup pin 2 enable */ 74 #define PMU_CS0_WUPEN3 BIT(11) /*!< wakeup pin 3 enable */ 75 #define PMU_CS0_WUPEN4 BIT(12) /*!< wakeup pin 4 enable */ 76 #define PMU_CS0_WUPEN5 BIT(13) /*!< wakeup pin 5 enable */ 77 #define PMU_CS0_WUPEN7 BIT(15) /*!< wakeup pin 7 enable */ 78 #define PMU_CS0_HDRF BIT(16) /*!< high-driver ready flag */ 79 #define PMU_CS0_HDSRF BIT(17) /*!< high-driver switch ready flag */ 80 #define PMU_CS0_LDRF BITS(18,19) /*!< Low-driver mode ready flag */ 81 82 /* PMU_CTL1 */ 83 #define PMU_CTL1_DPMOD1 BIT(0) /*!< deep-sleep 1 mode enable */ 84 #define PMU_CTL1_DPMOD2 BIT(1) /*!< deep-sleep 2 mode enable */ 85 86 /* PMU_CS1 */ 87 #define PMU_CS1_DPF1 BIT(0) /*!< deep-sleep 1 mode status flag */ 88 #define PMU_CS1_DPF2 BIT(1) /*!< deep-sleep 2 mode status flag */ 89 90 /* constants definitions */ 91 /* PMU ldo definitions */ 92 #define PMU_LDO_NORMAL ((uint32_t)0x00000000U) /*!< LDO normal work when PMU enter deepsleep mode */ 93 #define PMU_LDO_LOWPOWER PMU_CTL0_LDOLP /*!< LDO work at low power status when PMU enter deepsleep mode */ 94 95 /* PMU low voltage detector threshold definitions */ 96 #define CTL0_LVDT(regval) (BITS(5,7)&((uint32_t)(regval)<<5)) 97 #define PMU_LVDT_0 CTL0_LVDT(0) /*!< voltage threshold is 2.1V */ 98 #define PMU_LVDT_1 CTL0_LVDT(1) /*!< voltage threshold is 2.3V */ 99 #define PMU_LVDT_2 CTL0_LVDT(2) /*!< voltage threshold is 2.4V */ 100 #define PMU_LVDT_3 CTL0_LVDT(3) /*!< voltage threshold is 2.6V */ 101 #define PMU_LVDT_4 CTL0_LVDT(4) /*!< voltage threshold is 2.7V */ 102 #define PMU_LVDT_5 CTL0_LVDT(5) /*!< voltage threshold is 2.9V */ 103 #define PMU_LVDT_6 CTL0_LVDT(6) /*!< voltage threshold is 3.0V */ 104 #define PMU_LVDT_7 CTL0_LVDT(7) /*!< voltage threshold is 3.1V */ 105 106 /* PMU low-driver mode when use low power LDO */ 107 #define CTL0_LDLP(regval) (BIT(10)&((uint32_t)(regval)<<10)) 108 #define PMU_NORMALDR_LOWPWR CTL0_LDLP(0) /*!< normal driver when use low power LDO */ 109 #define PMU_LOWDR_LOWPWR CTL0_LDLP(1) /*!< low-driver mode enabled when LDEN is 11 and use low power LDO */ 110 111 /* PMU low-driver mode when use normal power LDO */ 112 #define CTL0_LDNP(regval) (BIT(11)&((uint32_t)(regval)<<11)) 113 #define PMU_NORMALDR_NORMALPWR CTL0_LDNP(0) /*!< normal driver when use normal power LDO */ 114 #define PMU_LOWDR_NORMALPWR CTL0_LDNP(1) /*!< low-driver mode enabled when LDEN is 11 and use normal power LDO */ 115 116 /* PMU high-driver mode switch */ 117 #define CTL0_HDS(regval) (BIT(17)&((uint32_t)(regval)<<17)) 118 #define PMU_HIGHDR_SWITCH_NONE CTL0_HDS(0) /*!< no high-driver mode switch */ 119 #define PMU_HIGHDR_SWITCH_EN CTL0_HDS(1) /*!< high-driver mode switch */ 120 121 /* low-driver mode in deep-sleep/deep-sleep 1/deep-sleep 2 mode */ 122 #define PMU_LOWDRIVER_DISABLE ((uint32_t)0x00000000U) /*!< low-driver mode disable in deep-sleep/deep-sleep 1/deep-sleep 2 mode */ 123 #define PMU_LOWDRIVER_ENABLE PMU_CTL0_LDEN /*!< low-driver mode enable in deep-sleep/deep-sleep 1/deep-sleep 2 mode */ 124 125 /* PMU WKUP pin definitions */ 126 #define PMU_WAKEUP_PIN0 PMU_CS0_WUPEN0 /*!< WKUP Pin 0 (PA0) enable */ 127 #define PMU_WAKEUP_PIN1 PMU_CS0_WUPEN1 /*!< WKUP Pin 1 (PC13) enable */ 128 #define PMU_WAKEUP_PIN2 PMU_CS0_WUPEN2 /*!< WKUP Pin 2 (PE6) enable */ 129 #define PMU_WAKEUP_PIN3 PMU_CS0_WUPEN3 /*!< WKUP Pin 3 (PA2) enable */ 130 #define PMU_WAKEUP_PIN4 PMU_CS0_WUPEN4 /*!< WKUP Pin 4 (PC5) enable */ 131 #define PMU_WAKEUP_PIN5 PMU_CS0_WUPEN5 /*!< WKUP Pin 5 (PB5) enable */ 132 #define PMU_WAKEUP_PIN6 PMU_CS0_WUPEN6 /*!< WKUP Pin 6 (PB15) enable */ 133 #define PMU_WAKEUP_PIN7 PMU_CS0_WUPEN7 /*!< WKUP Pin 7 (PF8) enable */ 134 135 /* PMU low power mode ready flag definitions */ 136 #define CS0_LDRF(regval) (BITS(18,19)&((uint32_t)(regval)<<18)) 137 #define PMU_LDRF_NORMAL CS0_LDRF(0) /*!< normal driver in deep-sleep/deep-sleep 1/deep-sleep 2 mode */ 138 #define PMU_LDRF_LOWDRIVER CS0_LDRF(3) /*!< low-driver mode in deep-sleep/deep-sleep 1/deep-sleep 2 mode */ 139 140 /* PMU flag definitions */ 141 #define PMU_FLAG_WAKEUP PMU_CS0_WUF /*!< wakeup flag status */ 142 #define PMU_FLAG_STANDBY PMU_CS0_STBF /*!< standby flag status */ 143 #define PMU_FLAG_LVD PMU_CS0_LVDF /*!< lvd flag status */ 144 #define PMU_FLAG_HDRF PMU_CS0_HDRF /*!< high-driver ready flag */ 145 #define PMU_FLAG_HDSRF PMU_CS0_HDSRF /*!< high-driver switch ready flag */ 146 #define PMU_FLAG_LDRF PMU_CS0_LDRF /*!< low-driver mode ready flag */ 147 #define PMU_FLAG_DEEPSLEEP_1 (BIT(31) | PMU_CS1_DPF1) /*!< deep-sleep 1 mode status flag */ 148 #define PMU_FLAG_DEEPSLEEP_2 (BIT(31) | PMU_CS1_DPF2) /*!< deep-sleep 2 mode status flag */ 149 150 /* PMU flag reset definitions */ 151 #define PMU_FLAG_RESET_WAKEUP ((uint8_t)0x00U) /*!< wakeup flag reset */ 152 #define PMU_FLAG_RESET_STANDBY ((uint8_t)0x01U) /*!< standby flag reset */ 153 #define PMU_FLAG_RESET_DEEPSLEEP_1 ((uint8_t)0x02U) /*!< deep-sleep 1 mode status flag reset */ 154 #define PMU_FLAG_RESET_DEEPSLEEP_2 ((uint8_t)0x03U) /*!< deep-sleep 2 mode status flag reset */ 155 156 /* PMU command constants definitions */ 157 #define WFI_CMD ((uint8_t)0x00U) /*!< use WFI command */ 158 #define WFE_CMD ((uint8_t)0x01U) /*!< use WFE command */ 159 160 /* function declarations */ 161 /* reset PMU registers */ 162 void pmu_deinit(void); 163 164 /* LVD functions */ 165 /* select low voltage detector threshold */ 166 void pmu_lvd_select(uint32_t lvdt_n); 167 /* disable PMU LVD */ 168 void pmu_lvd_disable(void); 169 170 /* functions of low-driver mode and high-driver mode */ 171 /* enable high-driver mode */ 172 void pmu_highdriver_mode_enable(void); 173 /* disable high-driver mode */ 174 void pmu_highdriver_mode_disable(void); 175 /* switch high-driver mode */ 176 void pmu_highdriver_switch_select(uint32_t highdr_switch); 177 /* enable low-driver mode in deep-sleep/deep-sleep 1/deep-sleep 2 mode */ 178 void pmu_lowdriver_mode_enable(void); 179 /* disable low-driver mode in deep-sleep/deep-sleep 1/deep-sleep 2 mode */ 180 void pmu_lowdriver_mode_disable(void); 181 /* in deep-sleep/deep-sleep 1/deep-sleep 2 mode, driver mode when use low power LDO */ 182 void pmu_lowpower_driver_config(uint32_t mode); 183 /* in deep-sleep/deep-sleep 1/deep-sleep 2 mode, driver mode when use normal power LDO */ 184 void pmu_normalpower_driver_config(uint32_t mode); 185 186 /* set PMU mode */ 187 /* PMU work in sleep mode */ 188 void pmu_to_sleepmode(uint8_t sleepmodecmd); 189 /* PMU work in deepsleep mode */ 190 void pmu_to_deepsleepmode(uint32_t ldo, uint32_t lowdrive, uint8_t deepsleepmodecmd); 191 /* PMU work in deepsleep mode 1 */ 192 void pmu_to_deepsleepmode_1(uint32_t ldo, uint32_t lowdrive, uint8_t deepsleepmode1cmd); 193 /* PMU work in deepsleep mode 2 */ 194 void pmu_to_deepsleepmode_2(uint32_t ldo, uint32_t lowdrive, uint8_t deepsleepmode2cmd); 195 /* PMU work in standby mode */ 196 void pmu_to_standbymode(uint8_t standbymodecmd); 197 /* enable PMU wakeup pin */ 198 void pmu_wakeup_pin_enable(uint32_t wakeup_pin); 199 /* disable PMU wakeup pin */ 200 void pmu_wakeup_pin_disable(uint32_t wakeup_pin); 201 202 /* backup related functions */ 203 /* enable backup domain write */ 204 void pmu_backup_write_enable(void); 205 /* disable backup domain write */ 206 void pmu_backup_write_disable(void); 207 208 /* flag functions */ 209 /* get flag state */ 210 FlagStatus pmu_flag_get(uint32_t flag); 211 /* clear flag bit */ 212 void pmu_flag_clear(uint32_t flag); 213 214 #endif /* GD32E50X_PMU_H */ 215
