1 /*! 2 \file gd32a50x_cmp.h 3 \brief definitions for the CMP 4 5 \version 2022-01-30, V1.0.0, firmware for GD32A50x 6 */ 7 8 /* 9 Copyright (c) 2022, GigaDevice Semiconductor Inc. 10 11 Redistribution and use in source and binary forms, with or without modification, 12 are permitted provided that the following conditions are met: 13 14 1. Redistributions of source code must retain the above copyright notice, this 15 list of conditions and the following disclaimer. 16 2. Redistributions in binary form must reproduce the above copyright notice, 17 this list of conditions and the following disclaimer in the documentation 18 and/or other materials provided with the distribution. 19 3. Neither the name of the copyright holder nor the names of its contributors 20 may be used to endorse or promote products derived from this software without 21 specific prior written permission. 22 23 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 24 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 25 WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 26 IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 27 INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 28 NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 29 PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 30 WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 32 OF SUCH DAMAGE. 33 */ 34 35 #ifndef GD32A50X_CMP_H 36 #define GD32A50X_CMP_H 37 38 #include "gd32a50x.h" 39 40 /* CMP definitions */ 41 #define CMP CMP_BASE + 0x00000000U /*!< CMP base address */ 42 43 /* registers definitions */ 44 #define CMP_CS REG32(CMP + 0x00000000U) /*!< CMP control and status register */ 45 46 /* bits definitions */ 47 /* CMP_CS */ 48 #define CMP_CS_EN BIT(0) /*!< CMP enable */ 49 #define CMP_CS_PM BITS(2,3) /*!< CMP mode */ 50 #define CMP_CS_MESEL BITS(4,6) /*!< CMP_IM external input selection */ 51 #define CMP_CS_MISEL BITS(7,9) /*!< CMP_IM internal input selection */ 52 #define CMP_CS_PSEL BITS(10,12) /*!< CMP_IP input selection */ 53 #define CMP_CS_OSEL BITS(13,14) /*!< CMP output selection */ 54 #define CMP_CS_PL BIT(15) /*!< polarity of CMP output */ 55 #define CMP_CS_HST BITS(16,17) /*!< CMP hysteresis */ 56 #define CMP_CS_BLK BITS(18,20) /*!< CMP output blanking source */ 57 #define CMP_CS_BEN BIT(22) /*!< scaler bridge enable bit */ 58 #define CMP_CS_SEN BIT(23) /*!< voltage input scaler */ 59 #define CMP_CS_OT BIT(30) /*!< CMP output */ 60 #define CMP_CS_LK BIT(31) /*!< CMP lock */ 61 62 /* constants definitions */ 63 /* operating mode */ 64 typedef enum { 65 CMP_HIGHSPEED = 0, /*!< high speed mode */ 66 CMP_MIDDLESPEED = 1, /*!< middle speed mode */ 67 CMP_LOWSPEED = 3 /*!< low speed mode */ 68 } operating_mode_enum; 69 70 /* inverting input */ 71 typedef enum { 72 CMP_1_4VREFINT = 0, /*!< VREFINT /4 input */ 73 CMP_1_2VREFINT = 8, /*!< VREFINT /2 input */ 74 CMP_3_4VREFINT = 16, /*!< VREFINT *3/4 input */ 75 CMP_VREFINT = 24, /*!< VREFINT input */ 76 CMP_DAC_OUT = 32, /*!< DAC_OUT input */ 77 CMP_IM_PC11 = 40, /*!< PC11*/ 78 CMP_IM_PC10 = 41, /*!< PC10 */ 79 CMP_IM_PB8 = 42, /*!< PB8 */ 80 CMP_IM_PA0 = 43, /*!< PA0 */ 81 CMP_IM_PA3 = 44, /*!< PA3 */ 82 CMP_IM_PA4 = 45, /*!< PA4 */ 83 CMP_IM_PA5 = 46, /*!< PA5 */ 84 CMP_IM_PA6 = 47, /*!< PA6 */ 85 } cmp_inverting_input_enum; 86 87 /* plus input */ 88 typedef enum { 89 CMP_IP_PC11 = 0, /*!< PC11*/ 90 CMP_IP_PC10, /*!< PC10 */ 91 CMP_IP_PB8, /*!< PB8 */ 92 CMP_IP_PA0, /*!< PA0 */ 93 CMP_IP_PA3, /*!< PA3 */ 94 CMP_IP_PA4, /*!< PA4 */ 95 CMP_IP_PA5, /*!< PA5 */ 96 CMP_IP_PA6 /*!< PA6 */ 97 } cmp_plus_input_enum; 98 99 /* hysteresis */ 100 typedef enum { 101 CMP_HYSTERESIS_NO = 0, /*!< output no hysteresis */ 102 CMP_HYSTERESIS_LOW, /*!< output low hysteresis */ 103 CMP_HYSTERESIS_MIDDLE, /*!< output middle hysteresis */ 104 CMP_HYSTERESIS_HIGH /*!< output high hysteresis */ 105 } cmp_hysteresis_enum; 106 107 /* output */ 108 typedef enum { 109 CMP_OUTPUT_NONE = 0, /*!< output no selection */ 110 CMP_OUTPUT_TIMER0IC0, /*!< TIMER 0 channel0 input capture */ 111 CMP_OUTPUT_TIMER7IC0 /*!< TIMER 7 channel0 input capture */ 112 } cmp_output_enum; 113 114 /* output inv */ 115 typedef enum { 116 CMP_OUTPUT_POLARITY_NOINVERTED = 0, /*!< output is not inverted */ 117 CMP_OUTPUT_POLARITY_INVERTED /*!< output is inverted */ 118 } cmp_output_inv_enum; 119 120 /* blanking_source*/ 121 typedef enum { 122 CMP_BLANKING_NONE = 0, /*!< no blanking */ 123 CMP_BLANKING_TIMER0_OC1, /*!< select TIMER0_CH1 as blanking source */ 124 CMP_BLANKING_TIMER7_OC1, /*!< select TIMER7_CH1 as blanking source */ 125 CMP_BLANKING_TIMER1_OC1 /*!< select TIMER1_CH1 as blanking source */ 126 } blanking_source_enum; 127 128 /* output state */ 129 typedef enum { 130 CMP_OUTPUTLEVEL_LOW = 0, /*!< the output is low */ 131 CMP_OUTPUTLEVEL_HIGH /*!< the output is high */ 132 } cmp_output_state_enum; 133 134 /* CMP mode */ 135 #define CS_CMPPM(regval) (BITS(2,3) & ((uint32_t)(regval) << 2)) 136 #define CS_CMPPM_HIGHSPEED CS_CMPPM(0) /*!< CMP mode high speed */ 137 #define CS_CMPPM_MIDDLESPEED CS_CMPPM(1) /*!< CMP mode middle speed */ 138 #define CS_CMPPM_LOWSPEED CS_CMPPM(3) /*!< CMP mode low speed */ 139 140 /* CMP input */ 141 /* IM input */ 142 #define CS_CMPMSEL(regval) (BITS(4,9) & ((uint32_t)(regval) << 4)) 143 #define CS_CMPMSEL_1_4VREFINT CS_CMPMSEL(0) /*!< CMP inverting internal input VREFINT *1/4 */ 144 #define CS_CMPMSEL_1_2VREFINT CS_CMPMSEL(8) /*!< CMP inverting internal input VREFINT *1/2 */ 145 #define CS_CMPMSEL_3_4VREFINT CS_CMPMSEL(16) /*!< CMP inverting internal input VREFINT *3/4 */ 146 #define CS_CMPMSEL_VREFINT CS_CMPMSEL(24) /*!< CMP inverting internal input VREFINT */ 147 #define CS_CMPMSEL_DAC_OUT CS_CMPMSEL(32) /*!< CMP inverting internal input DAC_OUT */ 148 #define CS_CMPMSEL_PC11 CS_CMPMSEL(40) /*!< CMP inverting external input PC11 */ 149 #define CS_CMPMSEL_PC10 CS_CMPMSEL(41) /*!< CMP inverting external input PC10 */ 150 #define CS_CMPMSEL_PB8 CS_CMPMSEL(42) /*!< CMP inverting external input PB8 */ 151 #define CS_CMPMSEL_PA0 CS_CMPMSEL(43) /*!< CMP inverting external input PA0 */ 152 #define CS_CMPMSEL_PA3 CS_CMPMSEL(44) /*!< CMP inverting external input PA3 */ 153 #define CS_CMPMSEL_PA4 CS_CMPMSEL(45) /*!< CMP inverting external input PA4 */ 154 #define CS_CMPMSEL_PA5 CS_CMPMSEL(46) /*!< CMP inverting external input PA5 */ 155 #define CS_CMPMSEL_PA6 CS_CMPMSEL(47) /*!< CMP inverting external input PA6 */ 156 157 /* IP input */ 158 #define CS_CMPPSEL(regval) (BITS(10,12) & ((uint32_t)(regval) << 10)) 159 #define CS_CMPPSEL_PC11 CS_CMPPSEL(0) /*!< CMP plus input PC11 */ 160 #define CS_CMPPSEL_PC10 CS_CMPPSEL(1) /*!< CMP plus input PC10 */ 161 #define CS_CMPPSEL_PB8 CS_CMPPSEL(2) /*!< CMP plus input PB8 */ 162 #define CS_CMPPSEL_PA0 CS_CMPPSEL(3) /*!< CMP plus input PA0 */ 163 #define CS_CMPPSEL_PA3 CS_CMPPSEL(4) /*!< CMP plus input PA3 */ 164 #define CS_CMPPSEL_PA4 CS_CMPPSEL(5) /*!< CMP plus input PA4 */ 165 #define CS_CMPPSEL_PA5 CS_CMPPSEL(6) /*!< CMP plus input PA5 */ 166 #define CS_CMPPSEL_PA6 CS_CMPPSEL(7) /*!< CMP plus input PA6 */ 167 168 /* CMP output selection */ 169 #define CS_CMPOSEL(regval) (BITS(13,14) & ((uint32_t)(regval) << 13)) 170 #define CS_CMPOSEL_NOSELECTION CS_CMPOSEL(0) /*!< CMP no output selection */ 171 #define CS_CMPOSEL_TIMER0IC0 CS_CMPOSEL(1) /*!< CMP as TIMER0 channel0 input capture source */ 172 #define CS_CMPOSEL_TIMER7IC0 CS_CMPOSEL(2) /*!< CMP as TIMER7 channel0 input capture source */ 173 174 /* CMP output polarity*/ 175 #define CS_CMPPL(regval) (BIT(15) & ((uint32_t)(regval) << 15)) 176 #define CS_CMPPL_NOT CS_CMPPL(0) /*!< CMP output not inverted */ 177 #define CS_CMPPL_INV CS_CMPPL(1) /*!< CMP output inverted */ 178 179 /* CMP hysteresis */ 180 #define CS_CMPHST(regval) (BITS(16,17) & ((uint32_t)(regval) << 16)) 181 #define CS_CMPHST_HYSTERESIS_NO CS_CMPHST(0) /*!< CMP output no hysteresis */ 182 #define CS_CMPHST_HYSTERESIS_LOW CS_CMPHST(1) /*!< CMP output low hysteresis */ 183 #define CS_CMPHST_HYSTERESIS_MIDDLE CS_CMPHST(2) /*!< CMP output middle hysteresis */ 184 #define CS_CMPHST_HYSTERESIS_HIGH CS_CMPHST(3) /*!< CMP output high hysteresis */ 185 186 /* CMP blanking suorce */ 187 #define CS_CMPBLK(regval) (BITS(18,20) & ((uint32_t)(regval) << 18)) 188 #define CS_CMPBLK_NOBLK CS_CMPBLK(0) /*!< CMP no blanking */ 189 #define CS_CMPBLK_TIMER0_OC1 CS_CMPBLK(1) /*!< CMP TIMER0 OC1 selected as blanking source */ 190 #define CS_CMPBLK_TIMER7_OC1 CS_CMPBLK(2) /*!< CMP TIMER7 OC1 selected as blanking source */ 191 #define CS_CMPBLK_TIMER1_OC1 CS_CMPBLK(4) /*!< CMP TIMER1 OC1 selected as blanking source */ 192 193 /* CMP bridge enable*/ 194 #define CS_CMPBEN(regval) (BIT(22) & ((uint32_t)(regval) << 22)) 195 #define CS_CMPBEN_DISABLE CS_CMPBEN(0) /*!< CMP bridge enable */ 196 #define CS_CMPBEN_ENABLE CS_CMPBEN(1) /*!< CMP bridge disable */ 197 198 /* CMP voltage scaler*/ 199 #define CS_CMPSEN(regval) (BIT(23) & ((uint32_t)(regval) << 23)) 200 #define CS_CMPSEN_DISABLE CS_CMPSEN(0) /*!< CMP voltage scaler enable */ 201 #define CS_CMPSEN_ENABLE CS_CMPSEN(1) /*!< CMP voltage scaler disable */ 202 203 /* CMP lock bit*/ 204 #define CS_CMPLK(regval) (BIT(31) & ((uint32_t)(regval) << 31)) 205 #define CS_CMPLK_DISABLE CS_CMPLK(0) /*!< CMP_CS bits are read-write */ 206 #define CS_CMPLK_ENABLE CS_CMPLK(1) /*!< CMP_CS bits are read-only */ 207 208 /* function declarations */ 209 /* initialization functions */ 210 /* deinitialize comparator */ 211 void cmp_deinit(void); 212 /* initialize comparator mode */ 213 void cmp_mode_init(operating_mode_enum operating_mode, cmp_inverting_input_enum inverting_input, cmp_plus_input_enum plus_input, 214 cmp_hysteresis_enum output_hysteresis); 215 /* initialize comparator output */ 216 void cmp_output_init(cmp_output_enum output_selection, cmp_output_inv_enum output_polarity); 217 /* initialize comparator blanking function */ 218 void cmp_outputblank_init(blanking_source_enum blanking_source_selection); 219 220 /* enable functions */ 221 /* enable comparator */ 222 void cmp_enable(void); 223 /* disable comparator */ 224 void cmp_disable(void); 225 /* enable the voltage scaler */ 226 void cmp_voltage_scaler_enable(void); 227 /* disable the voltage scaler */ 228 void cmp_voltage_scaler_disable(void); 229 /* enable the scaler bridge */ 230 void cmp_scaler_bridge_enable(void); 231 /* disable the scaler bridge */ 232 void cmp_scaler_bridge_disable(void); 233 /* lock the comparator */ 234 void cmp_lock_enable(void); 235 236 /* output functions */ 237 /* get output level */ 238 cmp_output_state_enum cmp_output_level_get(void); 239 240 #endif /* GD32A50X_CMP_H */ 241
