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Searched full:mco1_sel (Results 1 – 20 of 20) sorted by relevance

/Zephyr-latest/samples/boards/st/mco/boards/
Dnucleo_f446ze.overlay14 /* clocks = <&rcc STM32_SRC_HSI MCO1_SEL(0)>; */
15 /* clocks = <&rcc STM32_SRC_LSE MCO1_SEL(1)>; */
16 clocks = <&rcc STM32_SRC_HSE MCO1_SEL(2)>;
17 /* clocks = <&rcc STM32_SRC_PLL_P MCO1_SEL(3)>;*/
Dnucleo_f411re.overlay14 clocks = <&rcc STM32_SRC_HSI MCO1_SEL(0)>;
15 /* clocks = <&rcc STM32_SRC_LSE MCO1_SEL(1)>; */
16 /* clocks = <&rcc STM32_SRC_HSE MCO1_SEL(2)>; */
17 /* clocks = <&rcc STM32_SRC_PLL_P MCO1_SEL(3)>; */
Dnucleo_u5a5zj_q.overlay13 clocks = <&rcc STM32_SRC_LSE MCO1_SEL(MCO1_SEL_LSE)>;
Dnucleo_f429zi.overlay18 clocks = <&rcc STM32_SRC_HSE MCO1_SEL(MCO_SEL_HSE)>;
Dstm32f746g_disco.overlay17 clocks = <&rcc STM32_SRC_LSE MCO1_SEL(MCO1_SEL_LSE)>;
/Zephyr-latest/dts/bindings/clock/
Dst,stm32f1-clock-mco.yaml19 clocks = <&rcc STM32_SRC_LSE MCO1_SEL(7)>;
31 clocks = <&rcc STM32_SRC_PLL3CLK MCO1_SEL(9)>;
33 clocks = <&rcc STM32_SRC_PLL3CLK MCO1_SEL(11)>;
Dst,stm32-clock-mco.yaml17 clocks = <&rcc STM32_SRC_LSE MCO1_SEL(7)>;
/Zephyr-latest/include/zephyr/dt-bindings/clock/
Dstm32f10x_clock.h21 #undef MCO1_SEL /* Need to redefine generic F1 MCO_SEL for connectivity line devices. */
22 #define MCO1_SEL(val) STM32_MCO_CFGR(val, 0xF, 24, CFGR1_REG) macro
Dstm32f1_clock.h74 #define MCO1_SEL(val) STM32_MCO_CFGR(val, 0x7, 24, CFGR1_REG) macro
Dstm32f0_clock.h80 #define MCO1_SEL(val) STM32_MCO_CFGR(val, 0xF, 24, CFGR1_REG) macro
Dstm32f4_clock.h82 #define MCO1_SEL(val) STM32_MCO_CFGR(val, 0x3, 21, CFGR_REG) macro
Dstm32c0_clock.h79 #define MCO1_SEL(val) STM32_MCO_CFGR(val, 0x7, 24, CFGR1_REG) macro
Dstm32f3_clock.h72 #define MCO1_SEL(val) STM32_MCO_CFGR(val, 0x7, 24, CFGR_REG) macro
Dstm32f7_clock.h81 #define MCO1_SEL(val) STM32_MCO_CFGR(val, 0x3, 21, CFGR_REG) macro
Dstm32l4_clock.h109 #define MCO1_SEL(val) STM32_MCO_CFGR(val, 0xF, 24, CFGR_REG) macro
Dstm32h7rs_clock.h135 #define MCO1_SEL(val) STM32_MCO_CFGR(val, 0x7, 22, CFGR_REG) macro
Dstm32h7_clock.h139 #define MCO1_SEL(val) STM32_MCO_CFGR(val, 0xF, 22, CFGR_REG) macro
Dstm32u5_clock.h139 #define MCO1_SEL(val) STM32_MCO_CFGR(val, 0xF, 24, CFGR1_REG) macro
Dstm32h5_clock.h154 #define MCO1_SEL(val) STM32_MCO_CFGR(val, 0x7, 22, CFGR1_REG) macro
/Zephyr-latest/boards/shields/weact_ov2640_cam_module/boards/
Dmini_stm32h743.overlay34 clocks = <&rcc STM32_SRC_HSI48 MCO1_SEL(MCO1_SEL_HSI48)>;