Home
last modified time | relevance | path

Searched full:mchp (Results 1 – 25 of 50) sorted by relevance

12

/Zephyr-latest/drivers/pinctrl/
DKconfig.mec55 bool "Pin controller driver for MCHP MEC5 MCUs"
DKconfig.xec5 bool "Pin controller driver for MCHP XEC MCUs"
Dpinctrl_mchp_xec.c57 * MCHP calls repeater(keeper) mode.
102 /* MCHP XEC family is 32 pins per port */ in xec_config_pin()
Dpinctrl_mchp_mec5.c13 #include <zephyr/dt-bindings/pinctrl/mchp-xec-pinctrl.h>
/Zephyr-latest/drivers/eeprom/
DKconfig.xec7 bool "MCHP XEC EEPROM driver"
/Zephyr-latest/drivers/clock_control/
DKconfig.xec7 bool "MCHP XEC PCR clock control driver"
/Zephyr-latest/drivers/interrupt_controller/
DKconfig.xec7 bool "External EC Interrupt Aggregator (ECIA) Driver for MCHP MEC family of MCUs"
/Zephyr-latest/soc/microchip/mec/common/
Dpinctrl_soc.h20 #include <zephyr/dt-bindings/pinctrl/mchp-xec-pinctrl.h>
28 /* Type for MCHP XEC pin. */
DCMakeLists.txt16 set(MCHP_MEC_BIN_NAME ${CONFIG_KERNEL_BIN_NAME}.mchp.bin)
Dsoc_i2c.c31 * NOTE: MCHP MECxxxx data sheets specify GPIO pin numbers in octal.
/Zephyr-latest/soc/microchip/mec/
DKconfig10 bool "Create an unsigned output binary with MCHP MEC binary header"
19 authentication and all other Boot-ROM loader features. Refer to the MCHP
/Zephyr-latest/soc/microchip/mec/mec172x/
Dpower.c67 * Set MCHP Heavy sleep (PLL OFF when all CLK_REQ clear) and SLEEP_ALL in z_power_soc_deep_sleep()
164 * >= numerical priority. MCHP z_power_soc_(deep)_sleep sets PRIMASK=1 and BASEPRI=0
/Zephyr-latest/dts/arm/microchip/
Dmec172xnsz.dtsi14 #include <zephyr/dt-bindings/interrupt-controller/mchp-xec-ecia.h>
Dmec1727nsz.dtsi12 #include <zephyr/dt-bindings/interrupt-controller/mchp-xec-ecia.h>
Dmec172xnlj.dtsi14 #include <zephyr/dt-bindings/interrupt-controller/mchp-xec-ecia.h>
/Zephyr-latest/include/zephyr/dt-bindings/pinctrl/
Dmchp-xec-pinctrl.h54 * MCHP XEC documentation specifies pin numbers in octal.
/Zephyr-latest/drivers/timer/
Dmchp_mec5_ktimer.c21 BUILD_ASSERT(!IS_ENABLED(CONFIG_SMP), "MCHP MEC5 ktimer doesn't support SMP");
23 "MCHP MEC5 ktimer HW frequency is fixed at 32768");
26 BUILD_ASSERT(0, "MCHP MEC5 ktimer requires ARCH_HAS_CUSTOM_BUSY_WAIT");
/Zephyr-latest/soc/microchip/mec/mec15xx/
Dpower.c124 * preventing wake. MCHP z_power_soc_(deep)_sleep sets PRIMASK=1 and BASEPRI=0
/Zephyr-latest/dts/bindings/pinctrl/
Dmicrochip,mec5-pinctrl.yaml7 The MCHP XEC pin controller is a singleton node responsible for controlling
Dmicrochip,xec-pinctrl.yaml8 The MCHP XEC pin controller is a singleton node responsible for controlling
/Zephyr-latest/dts/arm/microchip/mec172x/
Dmec172x-vw-routing.dtsi11 mchp-xec-espi-vw-routing {
/Zephyr-latest/drivers/espi/
Despi_saf_mchp_xec.c303 * MCHP SAF supports 4KB, 32KB, and 64KB.
610 * MCHP SAF hardware supports a range of flash block erase
612 * 4KB must be supported. The MCHP SAF QMSPI HW interface only
Despi_saf_mchp_xec_v2.c17 #include <zephyr/dt-bindings/interrupt-controller/mchp-xec-ecia.h>
338 * MCHP SAF supports 4KB, 32KB, and 64KB.
782 * MCHP SAF hardware supports a range of flash block erase
784 * 4KB must be supported. The MCHP SAF QMSPI HW interface only
/Zephyr-latest/soc/microchip/mec/common/spigen/
Dmec_spi_gen.py256 default="zephyr.mchp.bin",
360 # NOTE: MCHP Production SPI Image Gen. pads with 0
/Zephyr-latest/samples/drivers/clock_control_xec/src/
Dmain.c12 #include <zephyr/dt-bindings/pinctrl/mchp-xec-pinctrl.h>

12