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/Zephyr-latest/dts/bindings/dma/
Dsilabs,ldma.yaml5 Silabs LDMA controller
7 The Silabs LDMA is a general-purpose direct memory access controller
13 compatible: "silabs,ldma"
/Zephyr-latest/samples/boards/microchip/mec172xevb_assy6906/qmspi_ldma/
Dsample.yaml2 description: mec172xevb_assy6906 QMSPI-LDMA testing
Dmec172xevb_assy6906.overlay65 compatible = "microchip,xec-qmspi-ldma";
/Zephyr-latest/drivers/spi/
DKconfig.xec_qmspi15 bool "Microchip XEC MEC17xx QMSPI LDMA driver"
Dspi_xec_qmspi_ldma.c670 /* Configure QMSPI such that QMSPI transfer FSM and LDMA FSM are synchronized.
672 * LDMA register(s). LDMA override length bit must NOT be set.
828 * Full-duplex always uses LDMA TX channel 0 and RX channel 0
941 LOG_ERR("XEC QMSPI-LDMA clock device not configured"); in qmspi_xec_init()
947 LOG_ERR("XEC QMSPI-LDMA enable clock source error %d", ret); in qmspi_xec_init()
953 LOG_ERR("XEC QMSPI-LDMA clock get rate error %d", ret); in qmspi_xec_init()
963 LOG_ERR("XEC QMSPI-LDMA pinctrl setup failed (%d)", ret); in qmspi_xec_init()
975 LOG_ERR("XEC QMSPI-LDMA init configure failed (%d)", ret); in qmspi_xec_init()
/Zephyr-latest/tests/drivers/spi/spi_loopback/boards/
Dmec172xevb_assy6906.overlay9 compatible = "microchip,xec-qmspi-ldma";
/Zephyr-latest/samples/drivers/spi_flash/boards/
Dmec172xevb_assy6906.overlay9 compatible = "microchip,xec-qmspi-ldma";
/Zephyr-latest/soc/microchip/mec/mec172x/reg/
Dmec172x_qspi.h376 /* LDMA Channel Control register */
386 /* LDMA unit(access) size: 1, 2, or 4 bytes */
392 /* LDMA increment memory start address by access size */
395 /* LDMA Channel (memory) Start address register */
398 /* LDMA Channel Length register */
/Zephyr-latest/dts/bindings/spi/
Dmicrochip,xec-qmspi-ldma.yaml7 compatible: "microchip,xec-qmspi-ldma"
/Zephyr-latest/drivers/dma/
Ddma_silabs_ldma.c134 /* Warning : High LDMA blockSize (high burst) mean a large transfer in dma_silabs_block_to_descriptor()
135 * without LDMA controller re-arbitration. in dma_silabs_block_to_descriptor()
152 /* In silabs LDMA, increment sign is managed with the transfer configuration in dma_silabs_block_to_descriptor()
155 * silabs LDMA. If increment sign is different in 2 block desc, then an in dma_silabs_block_to_descriptor()
/Zephyr-latest/boards/microchip/mec172xmodular_assy6930/
Dmec172xmodular_assy6930.dts180 compatible = "microchip,xec-qmspi-ldma";
/Zephyr-latest/boards/microchip/mec172xevb_assy6906/
Dmec172xevb_assy6906.dts202 compatible = "microchip,xec-qmspi-ldma";
/Zephyr-latest/soc/silabs/
DKconfig70 Set if the Linked Direct Memory Access (LDMA) HAL module is used.
/Zephyr-latest/boards/silabs/dev_kits/xg27_dk2602a/doc/
Dindex.rst50 | DMA | on-chip | ldma |
/Zephyr-latest/boards/silabs/radio_boards/slwrb4180a/doc/
Dindex.rst59 | DMA | on-chip | ldma |
/Zephyr-latest/boards/silabs/radio_boards/xg24_rb4187c/doc/
Dindex.rst56 | DMA | on-chip | ldma |
/Zephyr-latest/dts/arm/silabs/
Defr32bg2x.dtsi347 compatible = "silabs,ldma";
Defr32mg21.dtsi333 compatible = "silabs,ldma";
Defr32mg24.dtsi398 compatible = "silabs,ldma";
Defr32xg23.dtsi428 compatible = "silabs,ldma";
/Zephyr-latest/drivers/espi/
Despi_saf_mchp_xec_v2.c281 /* MEC172x SAF uses TX LDMA channel 0 in non-descriptor mode. in saf_qmspi_init()
282 * SAF HW writes QMSPI.Control and TX LDMA channel 0 registers in saf_qmspi_init()
284 * configure TX LDMA channel 0 control register. We believe SAF in saf_qmspi_init()
/Zephyr-latest/boards/silabs/dev_kits/xg24_dk2601b/doc/
Dindex.rst59 | DMA | on-chip | ldma |
/Zephyr-latest/boards/silabs/radio_boards/xg23_rb4210a/doc/
Dindex.rst56 | DMA | on-chip | ldma |
/Zephyr-latest/boards/silabs/dev_kits/sltb010a/doc/
Dindex.rst66 | DMA | on-chip | ldma |
/Zephyr-latest/doc/releases/
Drelease-notes-3.3.rst1642 - :dtcompatible:`microchip,xec-qmspi-ldma`: