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/Zephyr-latest/lib/hash/
Dhash_func32_murmur3.c10 static inline uint32_t murmur_32_scramble(uint32_t k) in murmur_32_scramble() argument
12 k *= 0xcc9e2d51; in murmur_32_scramble()
13 k = (k << 15) | (k >> 17); in murmur_32_scramble()
14 k *= 0x1b873593; in murmur_32_scramble()
16 return k; in murmur_32_scramble()
21 uint32_t k; in sys_hash32_murmur3() local
27 k = *(const uint32_t *)str; in sys_hash32_murmur3()
28 h ^= murmur_32_scramble(k); in sys_hash32_murmur3()
33 for (k = 0; n != 0; --n, ++str) { in sys_hash32_murmur3()
34 k <<= 8; in sys_hash32_murmur3()
[all …]
/Zephyr-latest/subsys/bluetooth/audio/
Dcsip_crypto.h37 * with a key K. The value of K depends on the transport on which the pairing
40 * If the pairing was performed on BR/EDR, K is equal to the Link Key shared by
42 * K = Link Key.
44 * If the pairing was performed on LE, the 64 LSBs of K correspond to the 64
47 * Part H, Section 2.1 in [2]), and the 64 MSBs of K correspond to the 64 MSBs
49 * K = LTK_64-127 || IRK_0-63
51 * @param k 16-byte key.
56 int bt_csip_sef(const uint8_t k[BT_CSIP_CRYPTO_KEY_SIZE], const uint8_t sirk[BT_CSIP_SIRK_SIZE],
63 * with a key K. The value of K depends on the transport on which the pairing
66 * If the pairing was performed on BR/EDR, K is equal to the Link Key shared by
[all …]
Dcsip_crypto.c63 * sih(k, r) = e(k, r') mod 2^24 in bt_csip_sih()
158 int bt_csip_sef(const uint8_t k[BT_CSIP_CRYPTO_KEY_SIZE], const uint8_t sirk[BT_CSIP_SIRK_SIZE], in bt_csip_sef()
161 const uint8_t m[] = {'S', 'I', 'R', 'K', 'e', 'n', 'c'}; in bt_csip_sef()
169 * sef(K, SIRK) = k1(K, s1("SIRKenc"), "csis") ^ SIRK in bt_csip_sef()
178 sys_memcpy_swap(k1_tmp, k, sizeof(k1_tmp)); in bt_csip_sef()
180 (void)memcpy(k1_tmp, k, sizeof(k1_tmp)); in bt_csip_sef()
182 LOG_DBG("BE: k %s", bt_hex(k1_tmp, sizeof(k1_tmp))); in bt_csip_sef()
209 int bt_csip_sdf(const uint8_t k[BT_CSIP_CRYPTO_KEY_SIZE], const uint8_t enc_sirk[BT_CSIP_SIRK_SIZE], in bt_csip_sdf()
217 * sdf(K, EncSIRK) = k1(K, s1("SIRKenc"), "csis") ^ EncSIRK in bt_csip_sdf()
221 return bt_csip_sef(k, enc_sirk, out_sirk); in bt_csip_sdf()
/Zephyr-latest/lib/libc/minimal/source/stdlib/
Dqsort.c14 * Normally parent is defined parent(k) = floor((k-1) / 2) but we can avoid a
15 * divide by noticing that floor((k-1) / 2) = ((k - 1) >> 1).
18 #define parent(k) (((k) - 1) >> 1) argument
20 * Normally left is defined left(k) = (2 * k + 1) but we can avoid a
21 * multiply by noticing that (2 * k + 1) = ((k << 1) + 1).
24 #define left(k) (((k) << 1) + 1) argument
27 * Normally right is defined right(k) = (2 * k + 2) but we can avoid a
28 * multiply by noticing that right(k) = left(k) + 1
30 #define right(k) (left(k) + 1) argument
32 #define A(k) ((uint8_t *)base + size * (k)) argument
/Zephyr-latest/scripts/pylib/twister/twisterlib/
Dconfig_parser.py158 for k, v in self.common.items():
159 if k == "extra_args":
161 extracted_common, d[k] = extract_fields_from_arg_list(
166 d[k] = copy.copy(v)
168 for k, v in self.scenarios[name].items():
169 if k == "extra_args":
174 if k in d:
175 if k == "filter":
176 d[k] = f"({d[k]}) and ({v})"
177 elif k not in ("extra_conf_files", "extra_overlay_confs",
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/Zephyr-latest/dts/bindings/pinctrl/
Dnxp,imx7d-pinctrl.yaml81 default: "100k"
84 - "5k"
85 - "47k"
86 - "100k"
89 Default of 100k as this is most common default register value for
91 01: 5K- 5K pull up resistor
92 10: 47K- 47K pull up resistor
93 11: 100K- 100K pull up resistor
Dnxp,mcux-rt-pinctrl.yaml103 default: "47k"
106 - "47k"
107 - "100k"
108 - "22k"
112 47k resistor selected as default due to this being the default pullup
115 01 PUS_1_47K_Ohm_Pull_Up — 47K Ohm Pull Up
116 10 PUS_2_100K_Ohm_Pull_Up — 100K Ohm Pull Up
117 11 PUS_2_22K_Ohm_Pull_Up — 22K Ohm Pull Up
121 default: "100k"
123 - "100k"
[all …]
/Zephyr-latest/dts/bindings/dac/
Dnxp,gau-dac.yaml35 - "62.5K"
36 - "125K"
37 - "250K"
38 - "500K"
39 default: "62.5K"
42 Default is "62.5K" because that is the reset value.
/Zephyr-latest/dts/bindings/pwm/
Dtelink,b91-pwm.yaml19 description: Default PWM Peripheral Clock frequency in Hz (is used if 32K Clock is disabled)
23 description: Enable 32K Source Clock for PWM Channel 0
27 description: Enable 32K Source Clock for PWM Channel 1
31 description: Enable 32K Source Clock for PWM Channel 2
35 description: Enable 32K Source Clock for PWM Channel 3
39 description: Enable 32K Source Clock for PWM Channel 4
43 description: Enable 32K Source Clock for PWM Channel 5
/Zephyr-latest/tests/arch/arm64/arm64_gicv3_its/boards/
Dfvp_base_revc_2xaemv8a.conf2 # - LPI prop table: global 1x64K aligned on 64K
3 # - LPI pend table: for each redistributor/cpu 1x64K aligned on 64K
4 # - Devices table: 128x4K aligned on 4K
5 # - Interrupt Collections table: 1x4K aligned on 4K
9 # Note, will need 64K HEAP_MEM per CPUs added.
/Zephyr-latest/boards/arm/fvp_base_revc_2xaemv8a/
DKconfig5 # - LPI prop table: global 1x64K aligned on 64K
6 # - LPI pend table: for each redistributor/cpu 1x64K aligned on 64K
7 # - Devices table: 128x4K aligned on 4K
8 # - Interrupt Collections table: 1x4K aligned on 4K
12 # Note, will need 64K HEAP_MEM per CPUs added.
/Zephyr-latest/boards/toradex/colibri_imx7d/
Dcolibri_imx7d-pinctrl.dtsi15 bias-pull-up-value = "100k";
27 bias-pull-up-value = "100k";
39 bias-pull-up-value = "100k";
51 bias-pull-up-value = "100k";
63 bias-pull-up-value = "100k";
74 bias-pull-up-value = "100k";
85 bias-pull-up-value = "100k";
96 bias-pull-up-value = "100k";
107 bias-pull-up-value = "100k";
/Zephyr-latest/samples/sensor/max6675/
DREADME.rst2 :name: MAX6675 K-thermocouple to digital converter
5 Get temperature from a MAX6675 K-thermocouple to digital converter (polling
12 cold-junction-compensated K-thermocouple to digital converter.
18 - K-thermocouple connected to MAX6675 T+/T- inputs
41 temperature fetch will fail if the K-thermocouple is not connected. This is
42 because MAX6675 is able to detect if the K-thermocouple is connected or not.
/Zephyr-latest/dts/arm/nxp/
Dnxp_lpc54xxx.dtsi53 * (note: reference manual says "up to <n>K")
56 * LPC540xx: RAMX: 192K, SRAM0: 64K, SRAM1: 32K, SRAM2: 32K, SRAM3: 32K, USBRAM: 8K
57 * LPC5410x: RAMX: ----, SRAM0: 64K, SRAM1: 32K, USBRAM: 8K @ 0x03400000
58 * LPC5411x: RAMX: 32K, SRAM0: 64K, SRAM1: 64K, SRAM2: 32K
83 * LPC54018: 192K @ 0x04000000
84 * LPC540xx: 192K @ 0x04000000
85 * LPC541xx: 32K @ 0x04000000
/Zephyr-latest/doc/connectivity/networking/api/
Dzperf.rst35 $ iperf -s -l 1K -u -V -B 2001:db8::2
41 $ iperf -s -l 1K -V -B 2001:db8::2
48 zperf udp upload 2001:db8::2 5001 10 1K 1M
55 zperf tcp upload 2001:db8::2 5001 10 1K 1M
63 zperf udp upload2 v6 10 1K 1M
70 zperf tcp upload2 v6 10 1K 1M
92 $ iperf -l 1K -u -V -c 2001:db8::1 -p 5001
99 $ iperf -l 1K -V -c 2001:db8::1 -p 5001
/Zephyr-latest/soc/xlnx/zynq7000/xc7zxxx/
DKconfig.soc21 28k logic cells, 2.1Mb block RAM, 800 DSP slices, up to 100 I/O pins.
28 74k logic cells, 3.3Mb block RAM, 160 DSP slices, up to 150 I/O pins,
36 85k logic cells, 4.9Mb block RAM, 220 DSP slices, up to 200 I/O pins.
43 125k logic cells, 9.3Mb block RAM, 400 DSP slices, up to 250 I/O pins,
51 275k logic cells, 17.6Mb block RAM, 900 DSP slices, up to 362 I/O pins,
59 350k logic cells, 19.1Mb block RAM, 900 DSP slices, up to 362 I/O pins,
67 444k logic cells, 26.5Mb block RAM, 2020 DSP slices, up to 400 I/O pins,
/Zephyr-latest/boards/technexion/pico_pi/
Dpico_pi-pinctrl.dtsi17 bias-pull-up-value = "100k";
29 bias-pull-up-value = "100k";
41 bias-pull-up-value = "100k";
53 bias-pull-up-value = "100k";
66 bias-pull-up-value = "100k";
79 bias-pull-up-value = "100k";
92 bias-pull-up-value = "100k";
/Zephyr-latest/dts/arm/st/u5/
Dstm32u5a9Xj.dtsi13 /* 768K + 64K + 832K + 832K */
/Zephyr-latest/boards/element14/warp7/
Dwarp7-pinctrl.dtsi17 bias-pull-up-value = "100k";
29 bias-pull-up-value = "100k";
41 bias-pull-up-value = "100k";
54 bias-pull-up-value = "100k";
67 bias-pull-up-value = "100k";
80 bias-pull-up-value = "100k";
/Zephyr-latest/samples/subsys/llext/edk/k-ext1/src/
Dmain.c26 printk("[k-ext1]Waiting event\n"); in tick_sub()
28 printk("[k-ext1]Got event, giving sem\n"); in tick_sub()
54 printk("[k-ext1]Waiting sem\n"); in start()
57 printk("[k-ext1]Got sem, reading channel\n"); in start()
59 printk("[k-ext1]Read val: %ld\n", l); in start()
/Zephyr-latest/samples/subsys/smf/smf_calculator/
Dsample.yaml7 # Sample takes ~300k on disco_l475_iot1 board, add 50k just in case.
8 # Ram usage is 70k on disco_l475_iot1 board with adafruit_2_8_tft_touch_v2.
/Zephyr-latest/samples/boards/espressif/flash_encryption/src/
Dmain.c36 for (int k = 0; k < 32; k++) { in main() local
37 buffer[k] = k; in main()
/Zephyr-latest/arch/arc/core/mpu/
Darc_mpu_v2_internal.h18 * 0x8 512 0x9 1k 0xA 2K 0xB 4K
19 * 0xC 8K 0xD 16K 0xE 32K 0xF 64K
20 * 0x10 128K 0x11 256K 0x12 512K 0x13 1M
/Zephyr-latest/soc/gaisler/gr716a/
Dlinker.ld22 bootprom (rx) : ORIGIN = 0x00000000, LENGTH = 4K
26 RAM (rw) : ORIGIN = 0x30000000, LENGTH = 64K
27 SRAM (x) : ORIGIN = 0x31000000, LENGTH = 128K
30 IDT_LIST (wx) : ORIGIN = 0xFFFFF7FF, LENGTH = 2K
/Zephyr-latest/boards/ezurio/bl5340_dvk/
Dbl5340_dvk_nrf5340_cpunet_common.dtsi43 /* 48K */
48 /* 88K */
53 /* 88K */
58 /* 32K */

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