1/*
2 * Copyright 2022 NXP
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7
8#include <nxp/nxp_imx7d_m4.dtsi>
9#include <nxp/nxp_imx/mimx7d-pinctrl.dtsi>
10
11&pinctrl {
12	uart2_default: uart2_default {
13		group0 {
14			pinmux = <&mx7d_pad_uart2_rx_data__uart2_dte_tx>,
15				<&mx7d_pad_uart2_tx_data__uart2_dte_rx>;
16			bias-pull-up;
17			bias-pull-up-value = "100k";
18			input-schmitt-enable;
19			slew-rate = "slow";
20			drive-strength = "x1";
21		};
22	};
23
24	uart6_default: uart6_default {
25		group0 {
26			pinmux = <&mx7d_pad_ecspi1_sclk__uart6_dce_rx>,
27				<&mx7d_pad_ecspi1_mosi__uart6_dce_tx>;
28			bias-pull-up;
29			bias-pull-up-value = "100k";
30			input-schmitt-enable;
31			slew-rate = "slow";
32			drive-strength = "x1";
33		};
34	};
35
36	i2c1_default: i2c1_default {
37		group0 {
38			pinmux = <&mx7d_pad_i2c1_scl__i2c1_scl>,
39				<&mx7d_pad_i2c1_sda__i2c1_sda>;
40			bias-pull-up;
41			bias-pull-up-value = "100k";
42			input-schmitt-enable;
43			slew-rate = "slow";
44			drive-strength = "x1";
45			input-enable;
46		};
47	};
48
49	i2c2_default: i2c2_default {
50		group0 {
51			pinmux = <&mx7d_pad_i2c2_scl__i2c2_scl>,
52				<&mx7d_pad_i2c2_sda__i2c2_sda>;
53			bias-pull-up;
54			bias-pull-up-value = "100k";
55			input-schmitt-enable;
56			slew-rate = "slow";
57			drive-strength = "x1";
58			input-enable;
59		};
60	};
61
62	i2c3_default: i2c3_default {
63		group0 {
64			pinmux = <&mx7d_pad_i2c3_scl__i2c3_scl>,
65				<&mx7d_pad_i2c3_sda__i2c3_sda>;
66			bias-pull-up;
67			bias-pull-up-value = "100k";
68			input-schmitt-enable;
69			slew-rate = "slow";
70			drive-strength = "x1";
71			input-enable;
72		};
73	};
74
75	i2c4_default: i2c4_default {
76		group0 {
77			pinmux = <&mx7d_pad_i2c4_scl__i2c4_scl>,
78				<&mx7d_pad_i2c4_sda__i2c4_sda>;
79			bias-pull-up;
80			bias-pull-up-value = "100k";
81			input-schmitt-enable;
82			slew-rate = "slow";
83			drive-strength = "x1";
84			input-enable;
85		};
86	};
87};
88