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/Zephyr-latest/boards/infineon/xmc47_relax_kit/
Darduino_r3_connector.dtsi28 <16 0 &gpio3 10 0>, /* D10 */
29 <17 0 &gpio3 8 0>, /* D11 */
30 <18 0 &gpio3 7 0>, /* D12 */
31 <19 0 &gpio3 9 0>, /* D13 */
32 <20 0 &gpio3 15 0>, /* D14 */
49 &gpio3 {
/Zephyr-latest/tests/drivers/stepper/drv8424/emul/boards/
Dnative_sim.overlay18 m0-gpios = <&gpio3 0 0>;
19 m1-gpios = <&gpio3 1 0>;
41 gpio3: gpio3 {
/Zephyr-latest/tests/drivers/stepper/drv8424/api/boards/
Dnative_sim.overlay18 m0-gpios = <&gpio3 0 0>;
19 m1-gpios = <&gpio3 1 0>;
41 gpio3: gpio3 {
/Zephyr-latest/boards/adi/apard32690/
Dapard32690_max32690_m4.dts62 gpio-map = <0 0 &gpio3 0 0>, /* A0 */
63 <1 0 &gpio3 1 0>, /* A1 */
64 <2 0 &gpio3 2 0>, /* A2 */
65 <3 0 &gpio3 3 0>, /* A3 */
66 <4 0 &gpio3 4 0>, /* A4 */
67 <5 0 &gpio3 5 0>, /* A5 */
107 &gpio3 {
/Zephyr-latest/tests/drivers/uart/uart_async_api/boards/
Desp32c6_devkitc.overlay11 input-enable; /* Connect GPIO2 and GPIO3 externally for testing */
15 output-enable; /* Connect GPIO2 and GPIO3 externally for testing */
/Zephyr-latest/boards/nxp/mimxrt1040_evk/
Dmimxrt1040_evk.dts99 <6 0 &gpio3 1 0>, /* D0 */
100 <7 0 &gpio3 0 0>, /* D1 */
102 <9 0 &gpio3 2 0>, /* D3 */
109 <16 0 &gpio3 13 0>, /* D10 */
110 <17 0 &gpio3 14 0>, /* D11 */
111 <18 0 &gpio3 15 0>, /* D12 */
112 <19 0 &gpio3 12 0>, /* D13 */
246 sdio-reset-gpios = <&gpio3 4 GPIO_ACTIVE_HIGH>;
247 w-disable-gpios = <&gpio3 2 GPIO_ACTIVE_HIGH>;
/Zephyr-latest/boards/nxp/frdm_mcxa156/
Dfrdm_mcxa156.dts40 gpios = <&gpio3 12 GPIO_ACTIVE_LOW>;
44 gpios = <&gpio3 13 GPIO_ACTIVE_LOW>;
48 gpios = <&gpio3 0 GPIO_ACTIVE_LOW>;
81 &gpio3 {
/Zephyr-latest/boards/toradex/verdin_imx8mm/
Dverdin_imx8mm_mimx8mm6_m4.dts35 gpios = <&gpio3 0 GPIO_ACTIVE_HIGH>;
40 &gpio3 {
/Zephyr-latest/dts/bindings/sound/
Dcirrus,cs47l63.yaml34 gpio3-gpios:
37 GPIO3 input with bus-keeper
/Zephyr-latest/boards/adi/max32690fthr/
Dmax32690fthr_max32690_m4.dts68 gpio-map = <0 0 &gpio3 0 0>, /* A0 */
69 <1 0 &gpio3 1 0>, /* A1 */
70 <2 0 &gpio3 4 0>, /* A2 */
108 &gpio3 {
/Zephyr-latest/boards/nxp/mimxrt1024_evk/
Dmimxrt1024_evk.dts88 <20 0 &gpio3 23 0>, /* D14 */
89 <21 0 &gpio3 22 0>; /* D15 */
188 scl-gpios = <&gpio3 22 GPIO_ACTIVE_HIGH>;
189 sda-gpios = <&gpio3 23 GPIO_ACTIVE_HIGH>;
239 cd-gpios = <&gpio3 19 GPIO_ACTIVE_LOW>;
240 pwr-gpios = <&gpio3 30 GPIO_ACTIVE_HIGH>;
/Zephyr-latest/boards/nxp/mimxrt1015_evk/
Dmimxrt1015_evk.dts38 gpios = <&gpio3 21 GPIO_ACTIVE_LOW>;
63 <6 0 &gpio3 1 0>, /* D0 */
64 <7 0 &gpio3 0 0>, /* D1 */
67 <10 0 &gpio3 2 0>, /* D4 */
/Zephyr-latest/drivers/gpio/
DKconfig.ads114s0x16 The GPIO port of the ADS114S0x (GPIO0 to GPIO3) is exposed as a
/Zephyr-latest/boards/nxp/mimxrt595_evk/
Dmimxrt595_evk_mimxrt595s_cm33.dts67 gpios = <&gpio3 17 0>;
117 <21 0 &gpio3 21 0>, /* Pin 21, RESET */
118 <22 0 &gpio3 18 0>, /* Pin 22, LPTE */
122 <29 0 &gpio3 19 0>, /* Pin 29, CTP_INT */
123 <32 0 &gpio3 15 0>, /* Pin 32, PWR_EN */
130 enable-gpios = <&gpio3 15 GPIO_ACTIVE_HIGH>;
297 * a given module. On this board, GPIO3 and GPIO4 are configured to support
300 &gpio3 {
/Zephyr-latest/dts/bindings/gpio/
Dx-powers,axp192-gpio.yaml13 [3] GPIO3
Draspberrypi,pico-header.yaml15 3 GPIO3 3V3_OUT -
Draspberrypi-40pins-header.yaml13 1 GPIO3/I2C1_SCL GND -
/Zephyr-latest/boards/adi/max32655evkit/
Dmax32655evkit_max32655_m4.dts51 gpios = <&gpio3 1 (GPIO_PULL_UP | GPIO_ACTIVE_LOW
100 &gpio3 {
/Zephyr-latest/boards/adi/max78002evkit/
Dmax78002evkit_max78002_m4.dts50 gpios = <&gpio3 1 (GPIO_PULL_UP | GPIO_ACTIVE_LOW
96 &gpio3 {
/Zephyr-latest/boards/nxp/mimxrt1020_evk/
Dmimxrt1020_evk.dts84 <20 0 &gpio3 23 0>, /* D14 */
85 <21 0 &gpio3 22 0>; /* D15 */
205 cd-gpios = <&gpio3 19 GPIO_ACTIVE_LOW>;
206 pwr-gpios = <&gpio3 24 GPIO_ACTIVE_HIGH>;
/Zephyr-latest/boards/nxp/imx8mp_evk/
Dimx8mp_evk_mimx8ml8_m7.dts33 &gpio3 {
Dimx8mp_evk_mimx8ml8_m7_ddr.dts33 &gpio3 {
/Zephyr-latest/boards/nxp/mimxrt1050_evk/
Dmimxrt1050_evk.dtsi107 <16 0 &gpio3 13 0>, /* D10 */
108 <17 0 &gpio3 14 0>, /* D11 */
109 <18 0 &gpio3 15 0>, /* D12 */
110 <19 0 &gpio3 12 0>, /* D13 */
/Zephyr-latest/boards/toradex/verdin_imx8mp/
Dverdin_imx8mp_mimx8ml8_m7.dts27 &gpio3 {
Dverdin_imx8mp_mimx8ml8_m7_ddr.dts27 &gpio3 {

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