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Searched full:gicr (Results 1 – 16 of 16) sorted by relevance

/Zephyr-latest/dts/bindings/interrupt-controller/
Darm,gic-v3.yaml15 <0x2f100000 0x200000>; /* GICR */
26 <0x2d000000 0x800000>, /* GICR 1: CPUs 0-31 */
27 <0x2e000000 0x800000>; /* GICR 2: CPUs 32-63 */
/Zephyr-latest/drivers/interrupt_controller/
Dintc_gic_common_priv.h10 /* Offsets from GICD base or GICR(n) SGI_base */
24 /* GICD GICR common access macros */
DKconfig.gic51 Some platforms only use aff0 to match mpdir and GICR.aff. With this
Dintc_gicv3_priv.h32 /* GICR registers offset from RD_base(n) */
/Zephyr-latest/dts/arm64/rockchip/
Drk3568.dtsi62 <0xfd460000 0xc0000>; /* GICR */
Drk3399.dtsi55 <0xfef00000 0xc0000>, /* GICR */
Drk3588s.dtsi71 <0xfe680000 0x100000>; /* GICR */
/Zephyr-latest/dts/arm64/nxp/
Dnxp_mimx91.dtsi49 <0x48040000 0xc0000>; /* GICR (RD_base + SGI_base) */
Dnxp_mimx95_a55.dtsi76 <0x48060000 0xc0000>; /* GICR (RD_base + SGI_base) */
Dnxp_mimx8mn_a53.dtsi69 <0x38880000 0xc0000>; /* GICR (RD_base + SGI_base) */
Dnxp_mimx8mm_a53.dtsi69 <0x38880000 0xc0000>; /* GICR (RD_base + SGI_base) */
Dnxp_mimx8mp_a53.dtsi63 <0x38880000 0xc0000>; /* GICR (RD_base + SGI_base) */
Dnxp_mimx93_a55.dtsi58 <0x48040000 0xc0000>; /* GICR (RD_base + SGI_base) */
/Zephyr-latest/dts/arm64/ti/
Dti_am62x_a53.dtsi48 <0x01880000 0xc0000>; /* GICR */
/Zephyr-latest/boards/arm/fvp_base_revc_2xaemv8a/
Dfvp_base_revc_2xaemv8a.dts85 <0x2f100000 0x200000>; // GICR
/Zephyr-latest/dts/arm64/intel/
Dintel_socfpga_agilex5.dtsi51 <0x1d060000 0x80000>; /* GICR */