| /Zephyr-latest/boards/nxp/imx93_evk/ |
| D | imx93_evk_mimx9352_m33_ddr.dts | 12 model = "NXP i.MX93 EVK board DDR variant";
15 zephyr,sram = &ddr;
19 ddr: memory@84000000 { label
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| D | imx93_evk_mimx9352_m33_ddr.yaml | 4 identifier: imx93_evk/mimx9352/m33/ddr
5 name: NXP i.MX93 EVK M33 DDR
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| D | board.yml | 8 - name: ddr
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| /Zephyr-latest/boards/nxp/imx95_evk/ |
| D | imx95_evk_mimx9596_m7_ddr.dts | 12 model = "NXP i.MX95 EVK board DDR variant";
15 zephyr,sram = &ddr;
19 ddr: memory@80000000 { label
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| D | imx95_evk_mimx9596_m7_ddr.yaml | 7 identifier: imx95_evk/mimx9596/m7/ddr
8 name: NXP i.MX95 EVK DDR variant
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| D | board.yml | 10 - name: ddr
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| /Zephyr-latest/soc/nxp/imx/imx8m/m7/ |
| D | mpu_regions.c | 55 * Region 4 DDR[0x4000_0000 - 0x8000_0000]:
58 MPU_REGION_ENTRY("DDR", REGION_DDR_BASE_ADDRESS,
63 * Non-cacheable area is provided in DDR memory, the DDR region [0x80000000 ~ 0x81000000]
69 * data section to be cacheable if the program running on DDR. The cacheable area base
73 * Region 5 DDR[0x8000_0000 - 0xBFFFFFFF]:
81 /* If run on DDR, configure text and data section to be cacheable */
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| D | linker.ld | 13 DDR (wx) : ORIGIN = 0x80400000, LENGTH = 0x00C00000
15 DDR (wx) : ORIGIN = 0x80000000, LENGTH = 0x01000000
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| /Zephyr-latest/boards/toradex/verdin_imx8mp/ |
| D | verdin_imx8mp_mimx8ml8_m7_ddr.yaml | 7 identifier: verdin_imx8mp/mimx8ml8/m7/ddr
8 name: Toradex Verdin iMX8M Plus (DDR)
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| D | board.yml | 8 - name: ddr
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| D | verdin_imx8mp_mimx8ml8_m7_ddr.dts | 18 /* DDR */
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| /Zephyr-latest/boards/nxp/imx8mp_evk/ |
| D | imx8mp_evk_mimx8ml8_m7_ddr.yaml | 7 identifier: imx8mp_evk/mimx8ml8/m7/ddr
8 name: NXP i.MX8M Plus EVK (DDR)
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| D | board.yml | 10 - name: ddr
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| D | imx8mp_evk_mimx8ml8_m7_ddr.dts | 17 /* DDR */
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| /Zephyr-latest/include/zephyr/drivers/i3c/ |
| D | hdr_ddr.h | 11 * @brief I3C HDR DDR API
12 * @defgroup i3c_hdr_ddr I3C HDR DDR API
28 * @brief Write a set amount of data to an I3C target device with HDR DDR.
56 * @brief Read a set amount of data from an I3C target device with HDR DDR.
84 * @brief Write then read data from an I3C target device with HDR DDR.
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| /Zephyr-latest/boards/udoo/udoo_neo_full/ |
| D | udoo_neo_full_mcimx6x_m4.dts | 14 * usually within DDR.
22 * usually within DDR.
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| /Zephyr-latest/dts/bindings/memory-controllers/ |
| D | sifive,fu740-c000-ddr.yaml | 7 compatible: "sifive,fu740-c000-ddr"
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| /Zephyr-latest/boards/phytec/phyboard_pollux/ |
| D | phyboard_pollux_mimx8ml8_m7_defconfig | 17 # y for DDR memory space
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| /Zephyr-latest/boards/snps/em_starterkit/ |
| D | arc_mpu_regions.c | 47 /* Region DDR RAM */
48 MPU_REGION_ENTRY("DDR RAM",
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| /Zephyr-latest/soc/ti/k3/am6x/m4/ |
| D | linker.ld | 16 } GROUP_LINK_IN(DDR)
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| /Zephyr-latest/boards/nxp/imx95_evk/doc/ |
| D | index.rst | 238 for the DDR variant, one should use the Makefile targets containing the ``ddr`` keyword.
244 ``imx95_evk/mimx9596/m7/ddr``. The main difference between them is the memory
246 data and DTCM for R/W data), while ``imx95_evk/mimx9596/m7/ddr`` uses DDR.
255 2. Building the :zephyr:code-sample:`hello_world` application for the DDR-based board
259 :board: imx95_evk/mimx9596/m7/ddr
270 while, for the ``imx95_evk/mimx9596/m7/ddr`` board, you should get the following output:
275 Hello World! imx95_evk/mimx9596/m7/ddr
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| /Zephyr-latest/boards/renesas/rzg3s_smarc/ |
| D | rzg3s_smarc_r9a08g045s33gbg_cm33.dts | 55 ddr: memory@60000000 { label
58 zephyr,memory-region = "DDR";
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| /Zephyr-latest/dts/bindings/qspi/ |
| D | nxp,s32-qspi.yaml | 30 - DDR
34 - Double Data Rate (DDR): sampling of incoming data occurs on both edges.
39 Set to align incoming data with 2x serial flash half clock, when in DDR
88 In case of Octal DDR mode, specifies whether a word unit composed of two
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| /Zephyr-latest/boards/renode/riscv32_virtual/support/ |
| D | riscv32_virtual.repl | 7 ddr: Memory.MappedMemory @ sysbus 0x80400000
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| /Zephyr-latest/boards/nxp/imx8mp_evk/doc/ |
| D | index.rst | 169 supported: ITCM and DDR). These are the memory mapping for A53 and M7:
182 | DDR | 0x80000000-0x803FFFFF | 0x80200000-0x803FFFFF | 0x80000000-0x801FFFFF | 2MB …
190 imx8mp_evk/mimx8ml8/m7/ddr for DDR).
212 DDR section in Programming and Debugging (M7)
227 and also need to reserve M4 DDR memory if using DDR code and sys address, and also
260 Extra Zephyr Kernel configure item for DDR Image:
262 If use remotepoc to boot DDR board (imx8mp_evk/mimx8ml8/m7/ddr), also need to enable
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