1 /* 2 * Copyright (c) 2021 Laird Connectivity 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7 #include <zephyr/devicetree.h> 8 #include <zephyr/arch/arm/cortex_m/arm_mpu_mem_cfg.h> 9 10 #define REGION_MASK_BASE_ADDRESS 0x00000000U 11 #define REGION_ITCM_BASE_ADDRESS 0x00000000U 12 #define REGION_QSPI_BASE_ADDRESS 0x08000000U 13 #define REGION_DTCM_BASE_ADDRESS 0x20000000U 14 #define REGION_DDR_BASE_ADDRESS 0x40000000U 15 #define REGION_DDR2_BASE_ADDRESS 0x80000000U 16 #if defined(CONFIG_CODE_DDR) 17 #define REGION_DDR_NONCACHE_BASE_ADDRESS 0x80000000U 18 #define REGION_DDR_NONCACHE_SIZE 0x00400000U 19 #endif 20 21 static const struct arm_mpu_region mpu_regions[] = { 22 /* 23 * Region 0 [0x0000_0000 - 0x4000_0000]: 24 * Memory with Device type, not executable, not shareable, non-cacheable. 25 */ 26 MPU_REGION_ENTRY("MASK", REGION_MASK_BASE_ADDRESS, 27 { ARM_MPU_RASR(1, ARM_MPU_AP_FULL, 28 0, 0, 0, 1, 0, ARM_MPU_REGION_SIZE_1GB) }), 29 30 /* 31 * Region 1 ITCM[0x0000_0000 - 0x0001_FFFF]: 32 * Memory with Normal type, not shareable, non-cacheable 33 */ 34 MPU_REGION_ENTRY("ITCM", REGION_ITCM_BASE_ADDRESS, 35 { ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 36 1, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_128KB) }), 37 38 /* 39 * Region 2 QSPI[0x0800_0000 - 0x0FFF_FFFF]: 40 * Memory with Normal type, not shareable, cacheable 41 */ 42 MPU_REGION_ENTRY("QSPI", REGION_QSPI_BASE_ADDRESS, 43 { ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 44 1, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_128MB) }), 45 46 /* 47 * Region 3 DTCM[0x2000_0000 - 0x2002_0000]: 48 * Memory with Normal type, not shareable, non-cacheable 49 */ 50 MPU_REGION_ENTRY("DTCM", REGION_DTCM_BASE_ADDRESS, 51 { ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 52 1, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_128KB) }), 53 54 /* 55 * Region 4 DDR[0x4000_0000 - 0x8000_0000]: 56 * Memory with Normal type, not shareable, non-cacheable 57 */ 58 MPU_REGION_ENTRY("DDR", REGION_DDR_BASE_ADDRESS, 59 { ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 60 1, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_1GB) }), 61 62 /* 63 * Non-cacheable area is provided in DDR memory, the DDR region [0x80000000 ~ 0x81000000] 64 * (please see the imx8mp-evk-rpmsg.dts) totally 16MB is reserved for CM7 core. You can put 65 * global or static uninitialized variables in NonCacheable section(initialized variables in 66 * NonCacheable.init section) to make them uncacheable. Since the base address of MPU region 67 * should be multiples of region size, to make it simple, the MPU region 5 set the address 68 * space 0x80000000 ~ 0xBFFFFFFF to be non-cacheable. Then MPU region 6 set the text and 69 * data section to be cacheable if the program running on DDR. The cacheable area base 70 * address should be multiples of its size in linker file, they can be modified per your 71 * needs. 72 * 73 * Region 5 DDR[0x8000_0000 - 0xBFFFFFFF]: 74 * Memory with Normal type, not shareable, non-cacheable 75 */ 76 MPU_REGION_ENTRY("DDR2", REGION_DDR2_BASE_ADDRESS, 77 { ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 78 1, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_1GB) }), 79 80 #if defined(CONFIG_CODE_DDR) 81 /* If run on DDR, configure text and data section to be cacheable */ 82 MPU_REGION_ENTRY("DDR_NONCACHE", REGION_DDR_NONCACHE_BASE_ADDRESS, 83 { ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 1, 84 0, 1, 1, 0, REGION_DDR_NONCACHE_SIZE) }), 85 #endif 86 }; 87 88 const struct arm_mpu_config mpu_config = { 89 .num_regions = ARRAY_SIZE(mpu_regions), 90 .mpu_regions = mpu_regions, 91 }; 92
