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/Zephyr-latest/dts/bindings/spi/
Dintel,penwell-spi.yaml31 Use GSPI chip select CS0 or CS1. GSPI 0, 1 & 2 instance supports both chip selects.
32 It can be configured with this DTS property. By default, CS0 is set.
34 0: CS0
Dmicrochip,xec-qmspi-ldma.yaml51 Use QMSPI CS0# or CS1#. Port 0 supports both chip selects.
52 Ports 1 and 2 implement CS0# only. Defaults to CS0#.
Dtelink,b91-spi.yaml24 cs0-pin:
Dmicrochip,xec-qmspi.yaml43 description: Use QMSPI CS0# or CS1#
/Zephyr-latest/soc/microchip/mec/mec172x/reg/
Dmec172x_espi_saf.h167 /* SAF CS0/CS1 Opcode A registers */
180 /* SAF CS0/CS1 Opcode B registers */
193 /* SAF CS0/CS1 Opcode C registers */
206 /* SAF CS0/CS1 registers */
449 /* SAF Flash CS0/CS1 Configuration Poll2 Mask registers */
500 /* SAF Config CS0 and CS1 Opcode registers */
519 /* SAF Clock Divider CS0 and CS1 registers */
/Zephyr-latest/boards/telink/tlsr9518adk80d/
Dtlsr9518adk80d.dts159 cs0-pin = "PSPI_CSN_PC4";
166 cs0-pin = "HSPI_CSN_PA1";
/Zephyr-latest/dts/bindings/gpio/
Datmel-xplained-header.yaml39 4 SPI(CS0) 5 6 SPI(MOSI) 5
Datmel-xplained-pro-header.yaml43 12 SPI(CS0) 15 16 SPI(MOSI) 13
/Zephyr-latest/drivers/espi/
Despi_saf_mchp_xec_v2.c267 /* Copy QMSPI frequency divider into SAF CS0 and CS1 QMSPI frequency in saf_qmspi_init()
268 * dividers. SAF HW uses CS0/CS1 divider register fields to overwrite in saf_qmspi_init()
270 * SAF CS0/CS1 SPI frequency dividers based on flash configuration. in saf_qmspi_init()
466 LOG_ERR("%s SAF CLKDIV CS0 bad freq MHz %u", in saf_flash_freq_cfg()
502 * CS0 OpA @ 0x4c or CS1 OpA @ 0x5C
503 * CS0 OpB @ 0x50 or CS1 OpB @ 0x60
504 * CS0 OpC @ 0x54 or CS1 OpC @ 0x64
507 * CS0: QMSPI descriptors 0-5 or CS1 QMSPI descriptors 6-11
508 * CS0 Descrs @ 0x58 or CS1 Descrs @ 0x68
509 * SAF CS0 QMSPI frequency dividers (read/all other) commands
[all …]
Despi_saf_mchp_xec.c384 * CS0 OpA @ 0x4c or CS1 OpA @ 0x5C
385 * CS0 OpB @ 0x50 or CS1 OpB @ 0x60
386 * CS0 OpC @ 0x54 or CS1 OpC @ 0x64
389 * CS0: QMSPI descriptors 0-5 or CS1 QMSPI descriptors 6-11
390 * CS0 Descrs @ 0x58 or CS1 Descrs @ 0x68
486 /* flash device connected to CS0 required */ in espi_saf_xec_configuration()
496 /* Program CS1 configuration (same as CS0 if only one device) */ in espi_saf_xec_configuration()
/Zephyr-latest/dts/riscv/telink/
Dtelink_b91.dtsi182 cs0-pin = "0";
194 cs0-pin = "0";
/Zephyr-latest/soc/microchip/mec/mec15xx/
Dsoc_espi_saf_v1.h137 * SAF Flash Config CS0/CS1 QMSPI descriptor indices register value
278 /* SAF Flash Config CS0 QMSPI descriptor indices */
/Zephyr-latest/boards/telink/tlsr9518adk80d/doc/
Dindex.rst128 - PSPI CS0: PC4, CLK: PC5, MISO: PC6, MOSI: PC7
129 - HSPI CS0: PA1, CLK: PA2, MISO: PA3, MOSI: PA4
/Zephyr-latest/boards/atmel/sam0/samr34_xpro/doc/
Dindex.rst115 - SERCOM5 GPIO CS0 : PA23
/Zephyr-latest/drivers/spi/
Dspi_b91.c52 /* loop through all cs pins (cs0..cs2) */ in spi_b91_hw_cs_disable()
92 /* loop through all cs pins: cs0, cs1 and cs2 */ in spi_b91_config_cs()
Dspi_pw.c168 /* Enable chip select output CS0/CS1 */ in spi_pw_cs_ctrl_init()
176 /* Set chip select CS0 */ in spi_pw_cs_ctrl_init()
Dspi_xec_qmspi.c174 * NOTE: QMSPI can control two chip selects. At this time we use CS0# only.
/Zephyr-latest/soc/microchip/mec/mec172x/
Dsoc_espi_saf_v2.h161 * SAF Flash Config CS0/CS1 QMSPI descriptor indices register value
358 /* SAF Flash Config CS0 QMSPI descriptor indices */
/Zephyr-latest/include/zephyr/dt-bindings/pinctrl/
Dnrf-pinctrl.h157 /** EXMIF CS0 */
/Zephyr-latest/boards/microchip/mec1501modular_assy6885/doc/
Dindex.rst162 ``JP23 3-4`` pulls SHD SPI CS0# up to VTR2. MEC1501 Boot-ROM samples
163 SHD SPI CS0# and if high, it loads code from SHD SPI.
/Zephyr-latest/boards/microchip/mec15xxevb_assy6853/doc/
Dindex.rst160 ``JP96 1-2`` pulls SHD SPI CS0# up to VTR2. MEC1501 Boot-ROM samples
161 SHD SPI CS0# and if high, it loads code from SHD SPI.
/Zephyr-latest/boards/microchip/mec172xevb_assy6906/doc/
Dindex.rst159 ``JP7 1-2`` pulls SHD SPI CS0# up to VTR2. MEC172x Boot-ROM samples
160 SHD SPI CS0# and if high, it loads code from SHD SPI.
/Zephyr-latest/drivers/pinctrl/renesas/rcar/
Dpfc_r8a77951.c103 { RCAR_GP_PIN(1, 20), 24, 3 }, /* CS0 */
Dpfc_r8a77961.c103 { RCAR_GP_PIN(1, 20), 24, 3 }, /* CS0 */