| /Zephyr-Core-3.5.0/subsys/settings/src/ |
| D | settings_store.c | 27 void settings_src_register(struct settings_store *cs) in settings_src_register() argument
29 sys_slist_append(&settings_load_srcs, &cs->cs_next); in settings_src_register()
32 void settings_dst_register(struct settings_store *cs) in settings_dst_register() argument
34 settings_save_dst = cs; in settings_dst_register()
44 struct settings_store *cs; in settings_load_subtree() local
57 SYS_SLIST_FOR_EACH_CONTAINER(&settings_load_srcs, cs, cs_next) { in settings_load_subtree()
58 cs->cs_itf->csi_load(cs, &arg); in settings_load_subtree()
70 struct settings_store *cs; in settings_load_subtree_direct() local
84 SYS_SLIST_FOR_EACH_CONTAINER(&settings_load_srcs, cs, cs_next) { in settings_load_subtree_direct()
85 cs->cs_itf->csi_load(cs, &arg); in settings_load_subtree_direct()
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| D | settings_fcb.c | 30 static int settings_fcb_load(struct settings_store *cs,
32 static int settings_fcb_save(struct settings_store *cs, const char *name,
34 static void *settings_fcb_storage_get(struct settings_store *cs);
146 static int settings_fcb_load_priv(struct settings_store *cs, in settings_fcb_load_priv() argument
151 struct settings_fcb *cf = CONTAINER_OF(cs, struct settings_fcb, cf_store); in settings_fcb_load_priv()
189 static int settings_fcb_load(struct settings_store *cs, in settings_fcb_load() argument
193 cs, in settings_fcb_load()
324 static int settings_fcb_save_priv(struct settings_store *cs, const char *name, in settings_fcb_save_priv() argument
327 struct settings_fcb *cf = CONTAINER_OF(cs, struct settings_fcb, cf_store); in settings_fcb_save_priv()
367 static int settings_fcb_save(struct settings_store *cs, const char *name, in settings_fcb_save() argument
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| /Zephyr-Core-3.5.0/dts/bindings/spi/ |
| D | nxp,s32-spi.yaml | 17 num-cs:
37 spi-sck-cs-delay:
41 deactivating Chip Select at the stop of transfer. If CS remains
44 This value will affect to all inner CS signals of SPI module when active.
45 This value will not be applied for CS lines controlled by GPIO.
47 spi-cs-sck-delay:
51 of clock signal at the start of transfer. If CS remains asserted
54 This value will affect to all inner CS signals of SPI module when active.
55 This value will not be applied for CS lines controlled by GPIO.
57 spi-cs-cs-delay:
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| D | espressif,esp32-spi.yaml | 47 clk-as-cs:
50 Support to toggle the CS while the clock toggles
52 Output clock on CS line if CS is active
54 positive-cs:
56 description: Make CS positive during a transaction instead of negative
68 cs-setup-time:
74 cs-hold-time:
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| D | spi-controller.yaml | 21 cs-gpios:
26 corresponds to the child node that the CS gpio controls.
31 cs-gpios = <&gpio0 23 GPIO_ACTIVE_LOW>,
48 GPIO flags GPIO_ACTIVE_LOW. Similarly, "spi-device@1" has CS GPIO
58 SPI controllers with dedicated CS pins do not need to define
59 the cs-gpios property.
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| D | microchip,xec-qmspi.yaml | 48 description: Delay in system clocks from CS# assertion to first clock edge
53 description: Delay in system clocks from last clock edge to CS# de-assertion
58 description: Delay in system clocks from CS# de-assertion to driving HOLD# and WP#
63 description: Delay in system clocks from CS# de-assertion to CS# assertion
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| D | microchip,xec-qmspi-ldma.yaml | 57 Delay in QMSPI main clocks from CS# assertion to first clock edge.
64 Delay in QMSPI main clocks from last clock edge to CS# de-assertion.
71 Delay in QMSPI main clocks from CS# de-assertion to driving HOLD#
78 Delay in QMSPI main clocks from CS# de-assertion to CS# assertion.
85 Allows different frequencies for CS#0 and CS1# devices. This applies
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| D | intel,penwell-spi.yaml | 15 cs-gpios:
18 pw,cs-mode:
27 pw,cs-output:
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| /Zephyr-Core-3.5.0/tests/drivers/spi/dt_spec/src/ |
| D | main.c | 21 LOG_DBG("spi_cs.config.cs.gpio.port = %p", spi_cs.config.cs.gpio.port); in ZTEST()
22 LOG_DBG("spi_cs.config.cs.gpio.pin = %u", spi_cs.config.cs.gpio.pin); in ZTEST()
26 zassert_equal(spi_cs.config.cs.gpio.port, DEVICE_DT_GET(DT_NODELABEL(test_gpio)), ""); in ZTEST()
27 zassert_equal(spi_cs.config.cs.gpio.pin, 0x10, ""); in ZTEST()
33 LOG_DBG("spi_no_cs.config.cs.gpio.port = %p", spi_no_cs.config.cs.gpio.port); in ZTEST()
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| /Zephyr-Core-3.5.0/subsys/bluetooth/host/ |
| D | hci_common.c | 42 struct bt_hci_evt_cmd_status *cs; in bt_hci_cmd_status_create() local
44 buf = bt_hci_evt_create(BT_HCI_EVT_CMD_STATUS, sizeof(*cs)); in bt_hci_cmd_status_create()
46 cs = net_buf_add(buf, sizeof(*cs)); in bt_hci_cmd_status_create()
47 cs->status = status; in bt_hci_cmd_status_create()
48 cs->ncmd = 1U; in bt_hci_cmd_status_create()
49 cs->opcode = sys_cpu_to_le16(op); in bt_hci_cmd_status_create()
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| /Zephyr-Core-3.5.0/soc/xtensa/espressif_esp32/common/ |
| D | Kconfig.soc | 124 menu "PSRAM clock and cs IO for ESP32-DOWD"
135 int "PSRAM CS IO number"
139 The PSRAM CS IO can be any unused GPIO, user can config it based on hardware design. If user use
142 endmenu # PSRAM clock and cs IO for ESP32-DOWD
144 menu "PSRAM clock and cs IO for ESP32-D2WD"
155 int "PSRAM CS IO number"
162 endmenu # PSRAM clock and cs IO for ESP32-D2WD
164 menu "PSRAM clock and cs IO for ESP32-PICO"
167 int "PSRAM CS IO number"
171 The PSRAM CS IO can be any unused GPIO, user can config it based on hardware design.
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| /Zephyr-Core-3.5.0/include/zephyr/devicetree/ |
| D | spi.h | 28 * SPI bus controllers use the "cs-gpios" property for configuring
36 * cs-gpios = <&gpio1 10 GPIO_ACTIVE_LOW>,
50 * @return 1 if "spi" has a cs-gpios property, 0 otherwise
55 * @brief Number of chip select GPIOs in a SPI controller's cs-gpios property
61 * cs-gpios = <&gpio1 10 GPIO_ACTIVE_LOW>,
75 * @return Logical length of spi's cs-gpios property, or 0 if "spi" doesn't
76 * have a cs-gpios property
88 * cs-gpios = <&gpio1 10 GPIO_ACTIVE_LOW>,
130 * cs-gpios = <&gpio1 10 GPIO_ACTIVE_LOW>,
171 * cs-gpios = <&gpio1 10 GPIO_ACTIVE_LOW>,
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| /Zephyr-Core-3.5.0/drivers/spi/ |
| D | spi_b91.c | 46 /* disable hardware cs flow control */
51 /* loop through all cs pins (cs0..cs2) */ in spi_b91_hw_cs_disable()
53 /* get CS pin defined in device tree */ in spi_b91_hw_cs_disable()
56 /* if CS pin is defined in device tree */ in spi_b91_hw_cs_disable()
59 /* disable CS pin for PSPI */ in spi_b91_hw_cs_disable()
62 /* disable CS pin for MSPI */ in spi_b91_hw_cs_disable()
69 /* config cs flow control: hardware or software */
78 /* disable all hardware CS pins */ in spi_b91_config_cs()
91 /* loop through all cs pins: cs0, cs1 and cs2 */ in spi_b91_config_cs()
93 /* get cs pin defined in device tree */ in spi_b91_config_cs()
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| /Zephyr-Core-3.5.0/soc/arm/atmel_sam0/common/ |
| D | soc_samr3x_radio_off.c | 15 const struct gpio_dt_spec cs = GPIO_DT_SPEC_GET(DT_NODELABEL(sercom4), cs_gpios); in radio_off_setup() local
17 if (!gpio_is_ready_dt(&reset) || !gpio_is_ready_dt(&cs)) { in radio_off_setup()
26 ret = gpio_pin_configure_dt(&cs, GPIO_OUTPUT_INACTIVE); in radio_off_setup()
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| /Zephyr-Core-3.5.0/boards/shields/x_nucleo_idb05a1/doc/ |
| D | index.rst | 20 but CS and SCK signals are not the standard Arduino SPI_CS and SPI_SCK signals.
37 Also shield expects SPI CS to be available on Arduino pin A1 instead of usual
38 Arduino UNO R3 SPI CS D10.
39 This is not a problem as CS signal is software driven gpio on Arduino A1
40 see cs-gpios in x_nucleo_idb05a1.overlay
50 - CS: To use D10 instead of A1, remove R2 and add R7
55 The stm32mp157c_dk2 board is known to need those CS/IRQ pin modifications
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| /Zephyr-Core-3.5.0/samples/drivers/spi_bitbang/src/ |
| D | main.c | 23 struct spi_cs_control *cs) in test_basic_write_9bit_words() argument
30 config.cs = *cs; in test_basic_write_9bit_words()
50 struct spi_cs_control *cs) in test_9bit_loopback_partial() argument
57 config.cs = *cs; in test_9bit_loopback_partial()
89 void test_8bit_xfer(const struct device *dev, struct spi_cs_control *cs) in test_8bit_xfer() argument
96 config.cs = *cs; in test_8bit_xfer()
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| /Zephyr-Core-3.5.0/include/zephyr/arch/x86/intel64/ |
| D | syscall.h | 39 * loaded from LSTAR MSR, masks RFLAGS with the low 32 bits of EFER.SFMASK. CS
41 * for CS, +8 for SS)
43 * SYSRET loads RIP from RCX and RFLAGS from r11. CS and SS are set with
44 * values derived from STAR MSR bits 63:48 (+8 for CS, +16 for SS)
173 int cs; in arch_is_user_context() local
175 __asm__ volatile ("mov %%cs, %[cs_val]" : [cs_val] "=r" (cs)); in arch_is_user_context()
177 return (cs & 0x3) != 0; in arch_is_user_context()
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| /Zephyr-Core-3.5.0/boards/arm/mimxrt1060_evk/ |
| D | mimxrt1060_evk_hyperflash.dts | 35 cs-interval-unit = <1>;
36 cs-interval = <2>;
37 cs-hold-time = <0>;
38 cs-setup-time = <3>;
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| /Zephyr-Core-3.5.0/dts/bindings/mtd/ |
| D | nxp,imx-flexspi-device.yaml | 9 cs-interval-unit:
20 cs-interval:
28 cs-setup-time:
36 cs-hold-time:
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| /Zephyr-Core-3.5.0/include/zephyr/arch/x86/ |
| D | msr.h | 33 * 47:32 Kernel CS (SS = CS+8)
34 * 63:48 User CS (SS = CS+8)
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| /Zephyr-Core-3.5.0/dts/bindings/gpio/ |
| D | ti,boosterpack-header.yaml | 18 2 Analog 22 GND 39 GPIO 19 GPIO / SPI CS
24 8 GPIO 28 Analog 33 GPIO 13 GPIO / SPI CS
25 9 I2C SCL 29 32 GPIO 12 GPIO / SPI CS
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| /Zephyr-Core-3.5.0/samples/modules/chre/ |
| D | README.rst | 63 .. _`chre_api/chre/nanoapp.h`: https://cs.android.com/android/platform/superproject/+/master:system…
64 .. _`pal/audio.h`: https://cs.android.com/android/platform/superproject/+/master:system/chre/pal/in…
65 .. _`pal/gnss.h`: https://cs.android.com/android/platform/superproject/+/master:system/chre/pal/inc…
66 .. _`pal/sensor.h`: https://cs.android.com/android/platform/superproject/+/master:system/chre/pal/i…
67 .. _`pal/system.h`: https://cs.android.com/android/platform/superproject/+/master:system/chre/pal/i…
68 .. _`pal/wifi.h`: https://cs.android.com/android/platform/superproject/+/master:system/chre/pal/inc…
69 .. _`pal/wwan.h`: https://cs.android.com/android/platform/superproject/+/master:system/chre/pal/inc…
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| /Zephyr-Core-3.5.0/subsys/mgmt/ec_host_cmd/backends/ |
| D | ec_host_cmd_backend_shi.h | 20 * 1. - - AP asserts chip select (CS#)
22 * 3. - - EC starts handling CS# interrupt
31 * 11 - - EC processes CS# interrupt and sets up DMA for
64 * CS goes low. This macro has the Most Significant Bit set to zero,
65 * so SDO will not be driven high when CS goes low.
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| /Zephyr-Core-3.5.0/arch/x86/core/ |
| D | fatal.c | 48 bool z_x86_check_stack_bounds(uintptr_t addr, size_t size, uint16_t cs) in z_x86_check_stack_bounds() argument
66 } else if ((cs & 0x3U) == 0U && in z_x86_check_stack_bounds()
68 /* The low two bits of the CS register is the privilege in z_x86_check_stack_bounds()
112 static void unwind_stack(uintptr_t base_ptr, uint16_t cs) in unwind_stack() argument
138 sizeof(*frame), cs)) { in unwind_stack()
163 if ((esf->cs & 0x3) != 0) { in get_cr3()
192 LOG_ERR("RSP: 0x%016lx RFLAGS: 0x%016lx CS: 0x%04lx CR3: 0x%016lx", in dump_regs()
193 esf->rsp, esf->rflags, esf->cs & 0xFFFFU, get_cr3(esf)); in dump_regs()
200 unwind_stack(esf->rbp, esf->cs); in dump_regs()
211 LOG_ERR("EFLAGS: 0x%08x CS: 0x%04x CR3: 0x%08lx", esf->eflags, in dump_regs()
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| /Zephyr-Core-3.5.0/drivers/fpga/ |
| D | fpga_ice40.c | 24 * Note: When loading a bitstream, the iCE40 has a 'quirk' in that the CS
27 * CS polarity is normal (active low). Zephyr's SPI driver model currently
30 * The logical alternative would be to put the CS into GPIO mode, perform 3
31 * separate SPI transfers (inverting CS polarity as necessary) and then
150 volatile gpio_port_pins_t *clear, gpio_port_pins_t cs, in fpga_ice40_spi_send_data() argument
157 *clear |= cs; in fpga_ice40_spi_send_data()
181 *set |= cs; in fpga_ice40_spi_send_data()
213 gpio_port_pins_t cs; in fpga_ice40_load_gpio() local
222 cs = BIT(config->bus.config.cs.gpio.pin); in fpga_ice40_load_gpio()
243 gpio_pin_configure_dt(&config->bus.config.cs.gpio, GPIO_OUTPUT_HIGH) || in fpga_ice40_load_gpio()
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