24  * Note: When loading a bitstream, the iCE40 has a 'quirk' in that the CS
27  * CS polarity is normal (active low). Zephyr's SPI driver model currently
30  * The logical alternative would be to put the CS into GPIO mode, perform 3
31  * separate SPI transfers (inverting CS polarity as necessary) and then
150 				     volatile gpio_port_pins_t *clear, gpio_port_pins_t cs,  in fpga_ice40_spi_send_data()  argument
157 	*clear |= cs;  in fpga_ice40_spi_send_data()
181 	*set |= cs;  in fpga_ice40_spi_send_data()
213 	gpio_port_pins_t cs;  in fpga_ice40_load_gpio()  local
222 	cs = BIT(config->bus.config.cs.gpio.pin);  in fpga_ice40_load_gpio()
243 	      gpio_pin_configure_dt(&config->bus.config.cs.gpio, GPIO_OUTPUT_HIGH) ||  in fpga_ice40_load_gpio()
250 	*config->clear |= (creset | cs);  in fpga_ice40_load_gpio()
265 	*config->set |= cs;  in fpga_ice40_load_gpio()
274 	fpga_ice40_spi_send_data(config->mhz_delay_count, config->set, config->clear, cs, clk, pico,  in fpga_ice40_load_gpio()
299 	(void)gpio_pin_configure_dt(&config->bus.config.cs.gpio, GPIO_OUTPUT_HIGH);  in fpga_ice40_load_gpio()
341 	      gpio_pin_configure_dt(&config->bus.config.cs.gpio, GPIO_OUTPUT_HIGH);  in fpga_ice40_load_spi()
352 	ret = gpio_pin_configure_dt(&config->bus.config.cs.gpio, GPIO_OUTPUT_LOW);  in fpga_ice40_load_spi()
375 	ret = gpio_pin_configure_dt(&config->bus.config.cs.gpio, GPIO_OUTPUT_HIGH);  in fpga_ice40_load_spi()
391 	ret = gpio_pin_configure_dt(&config->bus.config.cs.gpio, GPIO_OUTPUT_LOW);  in fpga_ice40_load_spi()
407 	ret = gpio_pin_configure_dt(&config->bus.config.cs.gpio, GPIO_OUTPUT_HIGH);  in fpga_ice40_load_spi()
440 	(void)gpio_pin_configure_dt(&config->bus.config.cs.gpio, GPIO_OUTPUT_HIGH);  in fpga_ice40_load_spi()