1# Copyright 2022-2023 NXP
2# SPDX-License-Identifier: Apache-2.0
3
4description: NXP S32 SPI controller
5
6compatible: "nxp,s32-spi"
7
8include: [spi-controller.yaml, pinctrl-device.yaml]
9
10properties:
11  reg:
12    required: true
13
14  interrupts:
15    required: true
16
17  num-cs:
18    type: int
19    required: true
20    description: |
21      The number of the Chip Select signals.
22
23  clocks:
24    required: true
25
26  pinctrl-0:
27    required: true
28
29  pinctrl-names:
30    required: true
31
32  slave:
33    type: boolean
34    description: |
35      Select if the SPI module is intended to be used in slave mode.
36
37  spi-sck-cs-delay:
38    type: int
39    description: |
40      A delay in nanoseconds between the stop of clock signal and
41      deactivating Chip Select at the stop of transfer. If CS remains
42      asserted between transfer, this delay will be inserted between transfer.
43      If not set, the minimum supported delay is used.
44      This value will affect to all inner CS signals of SPI module when active.
45      This value will not be applied for CS lines controlled by GPIO.
46
47  spi-cs-sck-delay:
48    type: int
49    description: |
50      A delay in nanoseconds between activating Chip Select and the start
51      of clock signal at the start of transfer. If CS remains asserted
52      between transfer, this delay will be inserted between transfer.
53      If not set, the minimum supported delay is used.
54      This value will affect to all inner CS signals of SPI module when active.
55      This value will not be applied for CS lines controlled by GPIO.
56
57  spi-cs-cs-delay:
58    type: int
59    description: |
60      A delay in nanoseconds between deactivating Chip Select at the stop
61      of previous transfer and activating Chip Select at the start of
62      next transfer. If CS remains asserted between transfer, this delay
63      will not be inserted.
64      If not set, the minimum supported delay is used.
65      This value will affect to all inner CS signals of SPI module when active.
66      This value will not be applied for CS lines controlled by GPIO.
67