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/Zephyr-latest/dts/bindings/dma/
Dgd,gd32-dma-v1.yaml49 - bit 0-1: Depth of DMA's FIFO used by burst-transfer.
78 The behavior of burst transfer determines by data-width in the config cell,
79 burst-length in the dma_config struct, and fifo-threshold.
80 A single burst transfer transfers [(4 * fifo-threshold)] bytes using with DMA's FIFO.
81 Where (data-width * burst-length) must be multiple numbers of burst transfer size.
82 For example, In the case of data-width is 'byte' and burst-length is 8.
83 If the fifo-threshold is a 2-word case, it runs one burst transfer to transfer 8 bytes.
84 Or the fifo-threshold is a 4-word case, runs two times burst transfer to transferring 8 bytes each
/Zephyr-latest/dts/bindings/ethernet/
Dmicrochip,lan865x.yaml27 plca-burst-count:
29 description: Specify the PLCA burst count
30 plca-burst-timer:
32 description: Specify the PLCA burst timer value
Dsnps,dwcxgmac.yaml115 Programmable burst length range: 4,5,16,32,64,128,256
150 AXI Undefined Burst Length.
151 1: The AXI master can perform burst transfers that are equal to or less
152 than the maximum allowed burst length enabled.
153 0: The AXI master performs one of the following burst transfers: Burst
154 transfers of fixed burst lengths as indicated by the BLEN256, BLEN128,
159 AXI Burst Length 4.
161 can select a burst length of 4 on the AXI interface.
166 AXI Burst Length 8.
168 can select a burst length of 8 on the AXI interface.
[all …]
Dqca,ar8031.yaml15 to greatly save the power consumption between data packets burst.
/Zephyr-latest/dts/bindings/memory-controllers/
Drenesas,smartbond-nor-psram.yaml89 Read command for single/burst read accesses in auto mode. Default value is the opcode
96 Write command for single/burst write accesses in auto mode. Default value is the opcode
136 consideration by QSPIC2 so that it can split a burst read/write
141 the #CS line can be driven low in a write/read burst access
153 Number of dummy bytes to send for single/burst read access in auto mode.
175 Describes the mode of SPI bus during the address phase for single/burst
187 Describes the mode of SPI bus during the instruction phase for single/burst
199 Describes the mode of SPI bus during the data phase for single/burst
211 Describes the mode of SPI bus during the dummy bytes phase for single/burst
222 Describes the mode of SPI bus during the extra byte phase for single/burst
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Dst,stm32-fmc-nor-psram.yaml16 - Burst mode for synchronous accesses with configurable option to split burst
21 - Burst mode for synchronous accesses
106 * BURSTEN - Burst enable bit.
115 * CBURSTRW - Write burst enable.
167 in NOR Flash memories with synchronous burst mode enable
/Zephyr-latest/include/zephyr/drivers/dma/
Ddma_mcux_lpc.h37 /* HW trigger burst mode. When set, the hardware trigger will cause a burst
44 /* HW trigger burst power. Note that due to the size limit of the dma_slot
45 * field, the maximum transfer burst possible is 128. The hardware supports
Ddma_mcux_pxp.h24 * source burst length: height of source buffer in pixels
26 * dest burst length: height of destination buffer in pixels
/Zephyr-latest/drivers/i2s/
DKconfig.mcux26 int "I2S EDMA BURST SIZE"
29 I2S EDMA burst size in bytes.
/Zephyr-latest/dts/bindings/mipi-dsi/
Dnxp,imx-mipi-dsi.yaml48 - "non-burst-sync-pulse"
49 - "non-burst-sync-event"
50 - "burst"
Dnxp,mipi-dsi-2l.yaml47 - "non-burst-sync-pulse"
48 - "non-burst-sync-event"
49 - "burst"
/Zephyr-latest/drivers/memc/
Dmemc_mcux_flexspi_aps6408l.c52 /* Burst type/burst length mask (MR8[0:2]) */
57 #define APS_6408L_ROW_CROSS_EN 0x8 /* Enable linear burst reads to cross rows */
84 /* Read Data (Sync read, linear burst) */
91 /* Write Data (Sync write, linear burst) */
242 /* Enable RBX, burst length set to 1K byte wrap. in memc_flexspi_aps6408l_init()
243 * this will also enable boundary crossing for burst reads in memc_flexspi_aps6408l_init()
248 LOG_ERR("Could not enable RBX 1K burst length"); in memc_flexspi_aps6408l_init()
/Zephyr-latest/drivers/dma/
Ddma_pl330.h14 * Max burst length and max burst size for 32bit system with
17 * Burst length is encoded in following format for pl330
25 * Burst size is encoded in following format for pl330
Ddma_stm32_v1.c17 /* DMA burst length */
377 LOG_ERR("Memory burst size error," in stm32_dma_get_mburst()
378 "using single burst as default"); in stm32_dma_get_mburst()
403 LOG_ERR("Peripheral burst size error," in stm32_dma_get_pburst()
404 "using single burst as default"); in stm32_dma_get_pburst()
DKconfig.dw_axi_dmac36 int "max burst transaction length"
/Zephyr-latest/include/zephyr/dt-bindings/memory-controller/
Dstm32-fmc-nor-psram.h24 /* Burst Access Mode */
52 /* Write Burst */
Dstm32-fmc-sdram.h40 /* Burst read */
/Zephyr-latest/include/zephyr/drivers/
Ddma.h258 /** Source burst length in bytes */
260 /** Destination burst length in bytes */
750 * @brief Look-up generic burst index to be used in registers
758 * @param burst: number of bytes to be sent in a single burst
762 static inline uint32_t dma_burst_index(uint32_t burst) in dma_burst_index() argument
764 /* Check boundaries (max supported burst length is 256) */ in dma_burst_index()
765 if (burst < 1 || burst > 256) { in dma_burst_index()
766 return 0; /* Zero is the default (1 burst length) */ in dma_burst_index()
769 /* Ensure burst is a power of 2 */ in dma_burst_index()
770 if (!(burst & (burst - 1))) { in dma_burst_index()
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/Zephyr-latest/drivers/ethernet/dwc_xgmac/
Deth_dwc_xgmac_priv.h474 /* Mixed burst: AXI master can perform burst transfers that are equal to or
475 * less than the maximum allowed burst length programmed
478 /* burst length 4bytes */
480 /* burst length 8bytes */
482 /* burst length 16bytes */
484 /* burst length 32bytes */
486 /* burst length 64bytes */
488 /* burst length 128bytes */
490 /* burst length 256bytes */
493 * address-aligned burst transfers on Read and Write channels
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/Zephyr-latest/drivers/ethernet/
Deth_lan865x_priv.h48 uint8_t burst_count; /* PLCA burst count range: 0x0 to 0xFF */
49 uint8_t burst_timer; /* PLCA burst timer */
/Zephyr-latest/boards/nxp/mimxrt1010_evk/
Dinit.c13 * will fetch more data than each AHB burst requires to meet alignment in SystemInitHook()
/Zephyr-latest/dts/arm/xilinx/
Dzynqmp.dtsi118 amba-ahb-burst-length = <XLNX_GEM_AMBA_AHB_BURST_SINGLE>;
145 amba-ahb-burst-length = <XLNX_GEM_AMBA_AHB_BURST_SINGLE>;
172 amba-ahb-burst-length = <XLNX_GEM_AMBA_AHB_BURST_SINGLE>;
199 amba-ahb-burst-length = <XLNX_GEM_AMBA_AHB_BURST_SINGLE>;
/Zephyr-latest/samples/drivers/i2s/output/
DREADME.rst14 The sample will send a short burst of audio data, consisting of a sine wave.
/Zephyr-latest/subsys/bluetooth/controller/ll_sw/
Dlll_conn_iso.h16 uint64_t bn:4; /* Burst number (BN) */
20 uint8_t bn_curr:4; /* Current burst number */
/Zephyr-latest/tests/drivers/build_all/ethernet/
Dspi_devices.overlay135 plca-burst-count = <1>;
136 plca-burst-timer = <1>;

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