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/Zephyr-latest/drivers/mm/
Dmm_drv_common.h4 * SPDX-License-Identifier: Apache-2.0
18 * @brief Get the flags of mapped virtual address.
21 * a mapped virtual address. This is used internally for remapping.
23 * Behavior when providing unaligned address is undefined, this
24 * is assumed to be page aligned.
26 * @param virt Page-aligned virtual address
27 * @param[out] flags flags of mapped virtual address
30 * @retval -EINVAL if invalid arguments are provided
31 * @retval -EFAULT if virtual address is not mapped
36 * @brief Test if address is page-aligned
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Dmm_drv_intel_adsp_tlb.c4 * SPDX-License-Identifier: Apache-2.0
50 #define TLB_PADDR_MASK ((1 << TLB_PADDR_SIZE) - 1)
58 * @param vaddr Page-aligned virtual address.
63 return (POINTER_TO_UINT(vaddr) - CONFIG_KERNEL_VM_BASE) / in get_tlb_entry_idx()
78 * As the main memory is in cached address ranges, in sys_mm_drv_map_page()
79 * the cached physical address is needed to perform in sys_mm_drv_map_page()
87 /* Make sure inputs are page-aligned */ in sys_mm_drv_map_page()
90 ret = -EINVAL; in sys_mm_drv_map_page()
94 /* Check bounds of physical address space */ in sys_mm_drv_map_page()
97 ret = -EINVAL; in sys_mm_drv_map_page()
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Dmm_drv_intel_adsp.h4 * SPDX-License-Identifier: Apache-2.0
44 #define TLB_PADDR_MASK ((1 << TLB_PADDR_SIZE) - 1)
47 /* This is used to translate from TLB entry back to physical address. */
48 /* base address of TLB table */
52 ((ROUND_DOWN((hpsram_ebb_quantity) + 31u, 32u) / 32u) - 1u)
61 * Calculate TLB entry based on physical address.
63 * @param pa Page-aligned virutal address.
72 * Calculate physical address based on TLB entry.
75 * @return physcial address pointer.
87 * @param End address of staticaly allocated memory.
/Zephyr-latest/include/zephyr/drivers/mm/
Dsystem_mm.h4 * SPDX-License-Identifier: Apache-2.0
11 * This contains APIs for a system-wide memory management
30 * This contains APIs for a system-wide memory management
48 /** Write-through caching */
51 /** Full write-back caching */
55 #define SYS_MM_MEM_CACHE_MASK (BIT(3) - 1)
64 * Default should be read-only, no user, no exec.
69 /** Region will have read/write access (and not read-only) */
75 /** Region will be accessible to user mode (normally supervisor-only) */
91 * @brief Map one physical page into the virtual address space
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/Zephyr-latest/include/zephyr/kernel/
Dmm.h4 * SPDX-License-Identifier: Apache-2.0
36 /** Write-through caching. Used by certain drivers. */
39 /** Full write-back caching. Any RAM mapped wants this. */
48 #define K_MEM_CACHE_MASK (BIT(3) - 1)
55 * Default is read-only, no user, no exec
60 /** Region will have read/write access (and not read-only) */
66 /** Region will be accessible to user mode (normally supervisor-only) */
77 /** Region will be mapped to 1:1 virtual and physical address */
111 * Such memory is guaranteed to never produce a page fault due to page-outs
112 * or copy-on-write once the mapping call has returned. Physical page frames
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/Zephyr-latest/arch/arm/core/
Dvector_table.ld2 * Copyright (c) 2019 - 2020 Nordic Semiconductor ASA
4 * SPDX-License-Identifier: Apache-2.0
9 * In an MCU with VTOR, the VTOR.TBLOFF is set to the start address of the
16 /* VTOR bits 0:7 are reserved (RES0). This requires that the base address
17 * of the vector table is 64-word aligned.
21 /* VTOR bits 0:6 are reserved (RES0). This requires that the base address
22 * of the vector table is 32-word aligned.
34 * setting in any Cortex-M implementation (might not be required in every
35 * Cortex-M processor).
43 * For AArch32 (M), VTOR has Bits [6:0] = RES0. Thus, vector start address
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/Zephyr-latest/include/zephyr/kernel/internal/
Dmm.h4 * SPDX-License-Identifier: Apache-2.0
21 * @brief Address offset of permanent virtual mapping from physical address.
23 * This is the offset to subtract from a virtual address mapped in the
24 * kernel's permanent mapping of RAM, to obtain its physical address.
41 #define K_MEM_VIRT_OFFSET ((CONFIG_KERNEL_VM_BASE + CONFIG_KERNEL_VM_OFFSET) - \
48 * @brief Get physical address from virtual address.
52 * @param virt Virtual address
54 * @return Physical address.
56 #define K_MEM_PHYS_ADDR(virt) ((virt) - K_MEM_VIRT_OFFSET)
59 * @brief Get virtual address from physical address.
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/Zephyr-latest/include/zephyr/kernel/mm/
Ddemand_paging.h4 * SPDX-License-Identifier: Apache-2.0
21 * @defgroup mem-demand-paging Demand Paging APIs
74 * excluding the first and last (hence, NUM_SLOTS - 1).
85 * Evict a page-aligned virtual memory region to the backing store
90 * marked as available for mappings or page-ins.
99 * called by ISRs as the backing store may be in-use.
101 * @param addr Base page-aligned virtual address
102 * @param size Page-aligned data region size
104 * @retval -ENOMEM Insufficient space in backing store to satisfy request.
117 * called by ISRs as the backing store may be in-use.
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/Zephyr-latest/include/zephyr/drivers/
Dcache.h4 * SPDX-License-Identifier: Apache-2.0
31 * @brief Enable the d-cache
38 * @brief Disable the d-cache
45 * @brief Flush the d-cache
50 * @retval -ENOTSUP If not supported.
51 * @retval -errno Negative errno for other failures.
56 * @brief Invalidate the d-cache
61 * @retval -ENOTSUP If not supported.
62 * @retval -errno Negative errno for other failures.
67 * @brief Flush and Invalidate the d-cache
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/Zephyr-latest/include/zephyr/arch/
Dcache.h4 * SPDX-License-Identifier: Apache-2.0
31 * @brief Enable the d-cache
40 * @brief Disable the d-cache
49 * @brief Flush the d-cache
54 * @retval -ENOTSUP If not supported.
55 * @retval -errno Negative errno for other failures.
62 * @brief Invalidate the d-cache
67 * @retval -ENOTSUP If not supported.
68 * @retval -errno Negative errno for other failures.
75 * @brief Flush and Invalidate the d-cache
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/Zephyr-latest/soc/common/riscv-privileged/
Dvector.S2 * Copyright (c) 2017 Jean-Paul Etienne <fractalclone@gmail.com>
5 * SPDX-License-Identifier: Apache-2.0
37 * mtvec.base must be aligned to 64 bytes (this is done using
52 * address of the interrupt handler instead of an opcode containing a
55 * When an interrupt occurs in CLIC vectored mode, the address of the
57 * hardware. This time mtvt is used as the base address for the
68 * Set mtvec (Machine Trap-Vector Base-Address Register)
70 * address of _irq_vector_table to indicate that vectored mode
72 * the address so that base address of _irq_vector_table is used.
74 * NOTE: _irq_vector_table is 256-byte aligned. Incorrect alignment
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/Zephyr-latest/include/zephyr/arch/arm64/
Dtpidrro_el0.h4 * SPDX-License-Identifier: Apache-2.0
11 * Among other things, the tpidrro_el0 holds the address for the current
12 * CPU's struct _cpu instance. But such a pointer is at least 8-bytes
13 * aligned, and the address space is 48 bits max. That leaves plenty of
/Zephyr-latest/kernel/include/
Dkernel_arch_interface.h4 * SPDX-License-Identifier: Apache-2.0
11 * Not all architecture-specific defines are here, APIs that are used
30 * @defgroup arch-timing Architecture timing APIs
35 * Architecture-specific implementation of busy-waiting
45 * @defgroup arch-threads Architecture thread APIs
46 * @ingroup arch-interface
50 /** Handle arch-specific logic for setting up new threads
52 * The stack and arch-specific thread state variables must be set up
61 * The provided stack pointer is guaranteed to be properly aligned with respect
64 * randomization and thread-local storage.
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/Zephyr-latest/arch/x86/zefi/
Defi.ld4 * SPDX-License-Identifier: Apache-2.0
12 /* Pick a reasonable base address, EFI won't load us there anyway */
20 * need to be page-aligned and can be immediately after text/rodata */
23 /* Must be page-aligned or EFI balks */
/Zephyr-latest/drivers/flash/
Dflash_ambiq.c4 * SPDX-License-Identifier: Apache-2.0
29 BUILD_ASSERT((FLASH_WRITE_BLOCK_SIZE & (MIN_WRITE_SIZE - 1)) == 0,
60 if ((offset < 0) || offset >= SOC_NV_FLASH_SIZE || (SOC_NV_FLASH_SIZE - offset) < len) { in flash_ambiq_valid_range()
72 return -EINVAL; in flash_ambiq_read()
90 uint32_t aligned[FLASH_WRITE_BLOCK_SIZE / sizeof(uint32_t)] = {0}; in flash_ambiq_write() local
93 /* write address must be block size aligned and the write length must be multiple of block in flash_ambiq_write()
97 ((uint32_t)offset & (FLASH_WRITE_BLOCK_SIZE - 1)) || in flash_ambiq_write()
98 (len & (FLASH_WRITE_BLOCK_SIZE - 1))) { in flash_ambiq_write()
99 return -EINVAL; in flash_ambiq_write()
112 /* Make sure the source data is 4-byte aligned. */ in flash_ambiq_write()
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Dsoc_flash_xmc4xxx.c4 * SPDX-License-Identifier: Apache-2.0
35 struct flash_xmc4xxx_data *dev_data = dev->data; in flash_xmc4xxx_init()
37 k_sem_init(&dev_data->sem, 1, 1); in flash_xmc4xxx_init()
58 const struct flash_xmc4xxx_config *dev_config = dev->config; in flash_xmc4xxx_read()
60 if (offset < 0 || offset + len > dev_config->size) { in flash_xmc4xxx_read()
61 return -1; in flash_xmc4xxx_read()
63 memcpy(data, (void *)(dev_config->base + offset), len); in flash_xmc4xxx_read()
72 struct flash_xmc4xxx_data *dev_data = dev->data; in flash_xmc4xxx_write()
73 const struct flash_xmc4xxx_config *dev_config = dev->config; in flash_xmc4xxx_write()
75 uint32_t flash_addr = dev_config->base; in flash_xmc4xxx_write()
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/Zephyr-latest/doc/kernel/memory_management/
Dvirtual_memory.rst15 between physical and virtual memory address spaces, if demand paging
48 * :kconfig:option:`CONFIG_KERNEL_VM_BASE`: base address of virtual address space.
50 * :kconfig:option:`CONFIG_KERNEL_VM_SIZE`: size of virtual address space.
61 the virtual address space. This is useful for mapping device MMIO regions for
68 This is an overview of the memory map of the virtual memory address space.
73 .. code-block:: none
74 :emphasize-lines: 1, 3, 9, 22, 24
76 +--------------+ <- K_MEM_VIRT_RAM_START
77 | Undefined VM | <- architecture specific reserved area
78 +--------------+ <- K_MEM_KERNEL_VIRT_START
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/Zephyr-latest/include/zephyr/arch/arm/cortex_a_r/
Dtpidruro.h3 * SPDX-License-Identifier: Apache-2.0
10 * Among other things, the tpidruro holds the address for the current
11 * CPU's struct _cpu instance. But such a pointer is at least 4-bytes
12 * aligned. That leaves two of free bits for other purposes.
/Zephyr-latest/include/zephyr/
Dcache.h5 * SPDX-License-Identifier: Apache-2.0
48 * @brief Enable the d-cache
61 * @brief Disable the d-cache
74 * @brief Enable the i-cache
87 * @brief Disable the i-cache
100 * @brief Flush the d-cache
105 * @retval -ENOTSUP If not supported.
106 * @retval -errno Negative errno for other failures.
113 return -ENOTSUP; in sys_cache_data_flush_all()
117 * @brief Flush the i-cache
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/Zephyr-latest/soc/intel/intel_adsp/common/include/
Dintel_adsp_hda.h2 * SPDX-License-Identifier: Apache-2.0
29 /* Buffers must be 128 byte aligned, this mask enforces that */
35 /* Calculate base address of the stream registers */
56 /* Gateway Buffer Base Address */
107 * @param base Base address of the IP register block
132 * @param base Base address of the IP register block
143 * Sanity checks that the buffer address and size are valid and that the
150 * @param base Base address of the IP register block
153 * @param buf Buffer address to use for the shared FIFO. Must be in L2 and 128 byte aligned.
154 * @param buf_size Buffer size in bytes Must be 128 byte aligned
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/Zephyr-latest/doc/services/storage/disk/
Dnvme.rst16 - NVMe controller: :zephyr_file:`drivers/disk/nvme/nvme_controller.c`
17 - NVMe commands: :zephyr_file:`drivers/disk/nvme/nvme_cmd.c`
18 - NVMe namespace: :zephyr_file:`drivers/disk/nvme/nvme_namespace.c`
26 …more than 1 namespace (disk), it will be possible to raise the amount of built-in namespace support
42 .. code-block:: devicetree
44 #include <zephyr/dt-bindings/pcie/pcie.h>
48 compatible = "nvme-controller";
49 vendor-id = <VENDOR_ID>;
50 device-id = <DEVICE_ID>;
63 Note that NVME requires the target to support PCIe multi-vector MSI-X in order to function.
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/Zephyr-latest/arch/arm/core/cortex_m/
Drelay_vector_table.ld2 * Copyright (c) 2019 - 2020 Nordic Semiconductor ASA
4 * SPDX-License-Identifier: Apache-2.0
9 * In an MCU with VTOR, the VTOR.TBLOFF is set to the start address of the
15 /* VTOR bits 0:6 are reserved (RES0). This requires that the base address
16 * of the vector table is 32-word aligned.
25 * setting in any Cortex-M implementation (might not be required in every
26 * Cortex-M processor).
/Zephyr-latest/tests/lib/heap_align/src/
Dmain.c4 * SPDX-License-Identifier: Apache-2.0
20 * are returned low-address to high, and that freed blocks are merged
32 zassert_true(q != NULL, "first aligned allocation failed"); in check_heap_align()
33 zassert_true((((uintptr_t)q) & (align - 1)) == 0, "block not aligned"); in check_heap_align()
36 zassert_true(r != NULL, "second aligned allocation failed"); in check_heap_align()
37 zassert_true((((uintptr_t)r) & (align - 1)) == 0, "block not aligned"); in check_heap_align()
42 s = sys_heap_alloc(h, (heap_end - (uint8_t *)r) - size - 8); in check_heap_align()
53 p = sys_heap_alloc(h, heap_end - heap_start); in check_heap_align()
71 /* Heap starts where that first chunk was, and ends one 8-byte in ZTEST()
75 heap_end = heapmem + HEAP_SZ - 8; in ZTEST()
/Zephyr-latest/drivers/display/
DKconfig.mcux_dcnano_lcdif2 # SPDX-License-Identifier: Apache-2.0
54 hex "LCDIF framebuffer address"
56 Address of memory mapped external framebuffer.
57 Must be 128 byte aligned
/Zephyr-latest/soc/ite/ec/it8xxx2/
Dilm.c4 * SPDX-License-Identifier: Apache-2.0
20 * IT8xxx2 allows 4-kilobyte blocks of RAM be configured individually as either Instruction- or
26 * SRAM address register (SCARn{H,M,L}) are redirected to the corresponding ILM block in RAM.
32 * address range non-cacheable (which is appropriate because Flash has high latency but RAM is
42 BUILD_ASSERT((ILM_BLOCK_SIZE & (ILM_BLOCK_SIZE - 1)) == 0, "ILM_BLOCK_SIZE must be a power of two");
53 * SCAR registers contain 20-bit addresses in three registers, with one set
57 /* Bits 0..7 of address; SCARnL */
59 /* Bits 8..15 of address; SCARnM */
61 /* Bits 16..18 and 19 of address, plus the enable bit for the entire SCAR; SCARnH */
76 return ((uintptr_t)p & (ILM_BLOCK_SIZE - 1)) == 0; in is_block_aligned()
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