Lines Matching +full:address +full:- +full:aligned

2  * Copyright (c) 2017 Jean-Paul Etienne <fractalclone@gmail.com>
5  * SPDX-License-Identifier: Apache-2.0
37 	 * mtvec.base must be aligned to 64 bytes (this is done using
52 	 * address of the interrupt handler instead of an opcode containing a
55 	 * When an interrupt occurs in CLIC vectored mode, the address of the
57 	 * hardware. This time mtvt is used as the base address for the
68 	 * Set mtvec (Machine Trap-Vector Base-Address Register)
70 	 * address of _irq_vector_table to indicate that vectored mode
72 	 * the address so that base address of _irq_vector_table is used.
74 	 * NOTE: _irq_vector_table is 256-byte aligned. Incorrect alignment
77 	la t0, _irq_vector_table /* Load address of interrupt vector table */
96 	 * Set mtvec (Machine Trap-Vector Base-Address Register)