Searched full:axi (Results 1 – 25 of 64) sorted by relevance
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| /Zephyr-latest/dts/bindings/dma/ |
| D | xilinx,axi-dma.yaml | 5 Xilinx AXI DMA LogiCORE IP controller with compatibility string
6 generated for use of the DMA outside of the AXI Ethernet subsystem.
8 include: xilinx,axi-dma-base.yaml
10 compatible: "xlnx,axi-dma-1.00.a"
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| D | xilinx,eth-dma.yaml | 5 Xilinx AXI DMA LogiCORE IP controller with compatibility string
6 generated in use with the AXI Ethernet subsystem.
8 include: xilinx,axi-dma-base.yaml
10 # this is the compatible generated by Vitis for the AXI Ethernet subsystem
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| D | xilinx,axi-dma-base.yaml | 4 description: Xilinx AXI DMA LogiCORE IP controller
42 Handle to connected node, e.g., AXI Ethernet controller.
50 description: Handle to connected control node, e.g., AXI Ethernet controller
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| D | snps,designware-dma-axi.yaml | 4 description: Synopsys Designware axi DMA Controller node
6 compatible: "snps,designware-dma-axi"
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| D | brcm,iproc-pax-dma-v1.yaml | 4 description: Broadcom iProc PAX(PCIE<->AXI) DMA controller version 1
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| D | brcm,iproc-pax-dma-v2.yaml | 4 description: Broadcom iProc PAX(PCIE<->AXI) DMA controller version 2
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| /Zephyr-latest/drivers/watchdog/ |
| D | Kconfig.xlnx | 7 bool "Xilinx AXI Timebase WDT driver"
11 Enable the Xilinx AXI Timebase WDT driver.
16 bool "Expose HWINFO API in Xilinx AXI Timebase WDT driver"
20 Controls whether the Xilinx AXI Timebase WDT driver exposes a HWINFO
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| /Zephyr-latest/drivers/pwm/ |
| D | Kconfig.xlnx | 1 # Xilinx AXI Timer
7 bool "Xilinx AXI Timer driver"
11 Enable PWM support for the Xilinx AXI Timer v2.0 IP.
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| /Zephyr-latest/drivers/counter/ |
| D | Kconfig.xlnx | 1 # Xilinx AXI Timer
7 bool "Xilinx AXI Timer driver"
11 Enable counter support for the Xilinx AXI Timer v2.0 IP.
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| /Zephyr-latest/dts/bindings/ethernet/ |
| D | snps,dwcxgmac.yaml | 101 AXI Maximum Write Outstanding Request Limit.This value
102 limits the maximum outstanding request on the AXI write
108 AXI Maximum Read Outstanding Request Limit.This value
109 limits the maximum outstanding request on the AXI read
150 AXI Undefined Burst Length.
151 1: The AXI master can perform burst transfers that are equal to or less
153 0: The AXI master performs one of the following burst transfers: Burst
159 AXI Burst Length 4.
160 When this enabled and the mixed_burst is disabled, the AXI master
161 can select a burst length of 4 on the AXI interface.
[all …]
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| /Zephyr-latest/drivers/dma/ |
| D | Kconfig.dw_axi_dmac | 7 bool "DesignWare AXI DMA driver"
12 DesignWare AXI DMA driver.
45 update this flag to change the axi master interface data width
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| D | Kconfig.xilinx_axi_dma | 1 # Xilinx AXI DMA configuration options
7 bool "Xilinx AXI DMA LogiCORE IP driver"
11 DMA driver for Xilinx AXI DMAs, usually found on FPGAs.
29 The Xilinx AXI DMA uses a ring of in-memory DMA descriptors which reference
39 The AXI DMA driver currently allocates a single DMA descriptor for each RX transfer,
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| D | Kconfig.iproc_pax | 6 prompt "Broadcom PAX(PCIE<->AXI) DMA driver"
13 prompt "Broadcom PAX(PCIE<->AXI) DMA driver version 2"
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| D | dma_xilinx_axi_dma.h | 2 * @brief Definitions and non-standard functions for Xilinx AXI DMA.
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| D | dma_iproc_pax_v1.h | 84 /* dma desc AXI addr field */
100 struct axi_addr_desc axi; member
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| /Zephyr-latest/drivers/gpio/ |
| D | Kconfig.xlnx | 7 bool "Xilinx AXI GPIO driver"
11 Enable Xilinx AXI GPIO v2 driver.
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| /Zephyr-latest/drivers/spi/ |
| D | Kconfig.xlnx | 7 bool "Xilinx AXI Quad SPI driver"
12 Enable Xilinx AXI Quad SPI v3.2 driver.
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| /Zephyr-latest/drivers/i2c/ |
| D | Kconfig.xilinx_axi | 5 bool "Xilinx AXI I2C driver"
10 Enable the Xilinx AXI IIC Bus Interface driver.
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| /Zephyr-latest/dts/bindings/watchdog/ |
| D | xlnx,xps-timebase-wdt-1.00.a.yaml | 4 description: Xilinx AXI timebase WDT core
15 description: Reference to AXI clock for watchdog core
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| /Zephyr-latest/dts/arm/st/h7/ |
| D | stm32h7a3.dtsi | 112 /* System data RAM accessible over AXI bus: AXI SRAM1 in CD domain */
118 /* System data RAM accessible over AXI bus: AXI SRAM2 in CD domain */
125 /* System data RAM accessible over AXI bus: AXI SRAM3 in CD domain */
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| /Zephyr-latest/dts/bindings/i2c/ |
| D | xlnx,xps-iic-2.1.yaml | 4 description: Xilinx AXI IIC Bus Interface
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| D | xlnx,xps-iic-2.00.a.yaml | 4 description: Xilinx AXI IIC Bus Interface
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| /Zephyr-latest/dts/bindings/gpio/ |
| D | xlnx,xps-gpio-1.00.a-gpio2.yaml | 1 description: Xilinx AXI GPIO IP GPIO2 node
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| /Zephyr-latest/dts/bindings/pcie/endpoint/ |
| D | brcm,iproc-pcie-ep.yaml | 14 Register space for the memory mapped PAX(PCIe to AXI bridge) registers,
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| /Zephyr-latest/dts/bindings/pwm/ |
| D | xlnx,xps-timer-1.00.a-pwm.yaml | 1 description: Xilinx AXI Timer IP node (PWM controller)
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