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/Zephyr-latest/dts/bindings/clock/
Dnuvoton,npcx-pcc.yaml179 APB4 prescaler. It sets the APB4 bus frequency, APB4_CLK, by dividing
181 - APB4_CLK must be set to 8MHz <= APB4_CLK <= 50MHz.
182 - APB4_CLK must be an integer division (including 1) of CORE_CLK.
184 1, APB4_CLK = OFMCLK
185 2, APB4_CLK = OFMCLK / 2
186 3, APB4_CLK = OFMCLK / 3
187 4, APB4_CLK = OFMCLK / 4
188 5, APB4_CLK = OFMCLK / 5
189 6, APB4_CLK = OFMCLK / 6
190 7, APB4_CLK = OFMCLK / 7
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/Zephyr-latest/dts/bindings/i3c/
Dnuvoton,npcx-i3c.yaml16 apb4-prescaler = <3>; /* APB4_CLK runs at 30MHz */
/Zephyr-latest/drivers/clock_control/
Dclock_control_npcx.c190 "Invalid APB4_CLK setting");
/Zephyr-latest/dts/arm/nuvoton/npcx/
Dnpcx9.dtsi158 apb4-prescaler = <6>; /* APB4_CLK runs at 15MHz */
Dnpcx4.dtsi158 apb4-prescaler = <8>; /* APB4_CLK runs at 15MHz */
/Zephyr-latest/drivers/i3c/
Di3c_npcx.c113 #define BAMATCH_DIV 0x4 /* BAMATCH = APB4_CLK divided by four */
306 /* The clock of this counter is APB4_CLK divided by four */ in get_bus_available_match_val()
2458 LOG_DBG("APB4_CLK: %d", apb4_rate); in npcx_i3c_apply_cntlr_config()
2492 LOG_DBG("APB4_CLK: %d", apb4_rate); in npcx_i3c_apply_target_config()