| /Zephyr-latest/include/zephyr/dt-bindings/pinctrl/renesas/ |
| D | pinctrl-r8a77961.h | 3 * Copyright (c) 2023-2024 EPAM Systems
5 * SPDX-License-Identifier: Apache-2.0
10 #include "pinctrl-rcar-common.h"
13 #define PIN_NONE -1
22 #define PIN_D8 RCAR_GP_PIN(0, 8)
26 #define PIN_D12 RCAR_GP_PIN(0, 12)
38 #define PIN_A8 RCAR_GP_PIN(1, 8)
42 #define PIN_A12 RCAR_GP_PIN(1, 12)
67 #define PIN_PWM2_A RCAR_GP_PIN(2, 8)
71 #define PIN_AVB_LINK RCAR_GP_PIN(2, 12)
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| D | pinctrl-r8a77951.h | 4 * SPDX-License-Identifier: Apache-2.0
9 #include "pinctrl-rcar-common.h"
12 #define PIN_NONE -1
21 #define PIN_D8 RCAR_GP_PIN(0, 8)
25 #define PIN_D12 RCAR_GP_PIN(0, 12)
37 #define PIN_A8 RCAR_GP_PIN(1, 8)
41 #define PIN_A12 RCAR_GP_PIN(1, 12)
66 #define PIN_PWM2_A RCAR_GP_PIN(2, 8)
70 #define PIN_AVB_LINK RCAR_GP_PIN(2, 12)
81 #define PIN_SD1_DATA0 RCAR_GP_PIN(3, 8)
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| D | pinctrl-r8a779f0.h | 4 * SPDX-License-Identifier: Apache-2.0
9 #include "pinctrl-rcar-common.h"
12 #define PIN_NONE -1
21 #define PIN_SCK0 RCAR_GP_PIN(0, 8)
25 #define PIN_MSIOF0_RXD RCAR_GP_PIN(0, 12)
42 #define PIN_GP1_08 RCAR_GP_PIN(1, 8)
46 #define PIN_MMC_SD_CLK RCAR_GP_PIN(1, 12)
67 #define PIN_QSPI1_SPCLK RCAR_GP_PIN(2, 8)
71 #define PIN_QSPI0_MISO_IO1 RCAR_GP_PIN(2, 12)
84 #define PIN_TSN0_LINK RCAR_GP_PIN(3, 8)
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| /Zephyr-latest/samples/modules/cmsis_dsp/moving_average/ |
| D | sample.yaml | 7 - samples
9 - qemu_cortex_m0
10 - native_sim
12 - cmsis-dsp
17 - "Input\\[00\\]: 0 0 0 0 0 0 0 0 0 0 | Output\\[00\\]: 0.00"
18 - "Input\\[01\\]: 0 0 0 0 0 0 0 0 0 1 | Output\\[01\\]: 0.10"
19 - "Input\\[02\\]: 0 0 0 0 0 0 0 0 1 2 | Output\\[02\\]: 0.30"
20 - "Input\\[03\\]: 0 0 0 0 0 0 0 1 2 3 | Output\\[03\\]: 0.60"
21 - "Input\\[04\\]: 0 0 0 0 0 0 1 2 3 4 | Output\\[04\\]: 1.00"
22 - "Input\\[05\\]: 0 0 0 0 0 1 2 3 4 5 | Output\\[05\\]: 1.50"
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| /Zephyr-latest/boards/we/proteus3ev/ |
| D | we_proteus3ev_nrf52840-pinctrl.dtsi | 4 psels = <NRF_PSEL(UART_TX, 1, 8)>,
9 <NRF_PSEL(UART_CTS, 0, 12)>;
10 bias-pull-up;
16 psels = <NRF_PSEL(UART_TX, 1, 8)>,
19 <NRF_PSEL(UART_CTS, 0, 12)>;
20 low-power-enable;
27 <NRF_PSEL(TWIM_SCL, 1, 8)>;
34 <NRF_PSEL(TWIM_SCL, 1, 8)>;
35 low-power-enable;
41 psels = <NRF_PSEL(SPIM_SCK, 0, 12)>,
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| /Zephyr-latest/include/zephyr/dt-bindings/espi/ |
| D | npcx_espi.h | 4 * SPDX-License-Identifier: Apache-2.0
10 * Encode virtual wire information into a 16-bit unsigned.
12 * group = bits[11:8], Group number for VWEVMS or VWEVSM
13 * dir = bits[13:12], Direction for controller to target or target to controller
16 (((dir & 0x1) << 12) + ((group & 0xf) << 8) + (index & 0xff))
20 #define ESPI_NPCX_VW_EX_GROUP_NUM(e) (((e) >> 8) & 0xf)
21 #define ESPI_NPCX_VW_EX_DIR(e) (((e) >> 12) & 0x1)
32 #define NPCX_VWEVMS8 8
36 #define NPCX_VWEVMS_MAX 12
47 #define NPCX_VWEVSM8 8
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| /Zephyr-latest/dts/bindings/sensor/ |
| D | ti,ina219.yaml | 2 # SPDX-License-Identifier: Apache-2.0
8 include: [sensor-device.yaml, i2c-device.yaml]
11 lsb-microamp:
17 example: 100 -> ~3A
18 shunt-milliohm:
31 The default of 32V is the power-on reset value of the device.
35 - 0
36 - 1
42 0 = 1 -> ±40 mV
43 1 = /2 -> ±80 mV
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| /Zephyr-latest/tests/lib/cmsis_dsp/filtering/src/ |
| D | misc_f16.c | 3 * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved.
5 * SPDX-License-Identifier: Apache-2.0
17 #define REL_ERROR_THRESH (1.0e-4)
18 #define ABS_ERROR_THRESH (1.0e-3)
20 #define REL_ERROR_THRESH_LD (1.0e-3)
21 #define ABS_ERROR_THRESH_LD (1.0e-3)
60 DEFINE_CORRELATE_TEST(4, 8);
65 DEFINE_CORRELATE_TEST(5, 8);
70 DEFINE_CORRELATE_TEST(6, 8);
75 DEFINE_CORRELATE_TEST(9, 8);
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| D | misc_f32.c | 3 * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved.
5 * SPDX-License-Identifier: Apache-2.0
17 #define REL_ERROR_THRESH (1.0e-6)
18 #define ABS_ERROR_THRESH (1.0e-5)
19 #define REL_ERROR_THRESH_LD (1.0e-6)
20 #define ABS_ERROR_THRESH_LD (1.0e-6)
31 * refer to the CMSIS-DSP bug ARM-software/CMSIS-DSP#59. in test_arm_correlate_f32()
38 output = output_buf + 8; in test_arm_correlate_f32()
68 DEFINE_CORRELATE_TEST(4, 8);
73 DEFINE_CORRELATE_TEST(5, 8);
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| D | misc_q31.c | 3 * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved.
5 * SPDX-License-Identifier: Apache-2.0
30 * refer to the CMSIS-DSP bug ARM-software/CMSIS-DSP#59. in test_arm_correlate_q31()
37 output = output_buf + 8; in test_arm_correlate_q31()
64 DEFINE_CORRELATE_TEST(4, 8);
69 DEFINE_CORRELATE_TEST(5, 8);
74 DEFINE_CORRELATE_TEST(6, 8);
79 DEFINE_CORRELATE_TEST(9, 8);
84 DEFINE_CORRELATE_TEST(10, 8);
89 DEFINE_CORRELATE_TEST(11, 8);
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| /Zephyr-latest/soc/intel/apollo_lake/ |
| D | soc_gpio.h | 2 * Copyright (c) 2018-2019, Intel Corporation
4 * SPDX-License-Identifier: Apache-2.0
31 #define APL_GPIO_8 8
35 #define APL_GPIO_12 12
65 #define APL_GPIO_40 8
69 #define APL_GPIO_44 12
99 #define APL_GPIO_CNV_BRI_RSP 8
103 #define APL_GPIO_SVOD0_DATA 12
115 #define APL_GPIO_195 8
119 #define APL_GPIO_199 12
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| /Zephyr-latest/drivers/pinctrl/renesas/rcar/ |
| D | pfc_r8a779f0.c | 4 * SPDX-License-Identifier: Apache-2.0
10 #include <zephyr/dt-bindings/pinctrl/renesas/pinctrl-r8a779f0.h>
19 { RCAR_GP_PIN(0, 3), 12, 3 }, /* HTX0 */
20 { RCAR_GP_PIN(0, 2), 8, 3 }, /* HRX0 */
29 { RCAR_GP_PIN(0, 12), 16, 3 }, /* MSIOF0_RXD */
30 { RCAR_GP_PIN(0, 11), 12, 3 }, /* MSIOF0_SYNC */
31 { RCAR_GP_PIN(0, 10), 8, 3 }, /* CTS0_N */
33 { RCAR_GP_PIN(0, 8), 0, 3 }, /* SCK0 */
38 { RCAR_GP_PIN(0, 19), 12, 3 }, /* IRQ2 */
39 { RCAR_GP_PIN(0, 18), 8, 3 }, /* IRQ1 */
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| D | pfc_r8a77951.c | 2 * Copyright (c) 2021-2023 IoT.bzh
4 * SPDX-License-Identifier: Apache-2.0
9 #include <zephyr/dt-bindings/pinctrl/renesas/pinctrl-r8a77951.h>
18 { PIN_QSPI0_IO3, 12, 2 }, /* QSPI0_IO3 */
19 { PIN_QSPI0_SSL, 8, 2 }, /* QSPI0_SSL */
29 { PIN_RPC_INT_N, 12, 2 }, /* RPC_INT# */
30 { PIN_RPC_WP_N, 8, 2 }, /* RPC_WP# */
40 { PIN_AVB_RD3, 12, 3 }, /* AVB_RD3 */
41 { PIN_AVB_TX_CTL, 8, 3 }, /* AVB_TX_CTL */
51 { PIN_AVB_MDIO, 12, 3 }, /* AVB_MDIO */
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| D | pfc_r8a77961.c | 2 * Copyright (c) 2021-2023 IoT.bzh
4 * SPDX-License-Identifier: Apache-2.0
9 #include <zephyr/dt-bindings/pinctrl/renesas/pinctrl-r8a77961.h>
18 { PIN_QSPI0_IO3, 12, 2 }, /* QSPI0_IO3 */
19 { PIN_QSPI0_SSL, 8, 2 }, /* QSPI0_SSL */
29 { PIN_RPC_INT_N, 12, 2 }, /* RPC_INT# */
30 { PIN_RPC_WP_N, 8, 2 }, /* RPC_WP# */
40 { PIN_AVB_RD3, 12, 3 }, /* AVB_RD3 */
41 { PIN_AVB_TX_CTL, 8, 3 }, /* AVB_TX_CTL */
51 { PIN_AVB_MDIO, 12, 3 }, /* AVB_MDIO */
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| /Zephyr-latest/drivers/ipm/ |
| D | ipm_nrfx_ipc.h | 4 * SPDX-License-Identifier: Apache-2.0
13 * Message channels are one-way connections between cores.
19 * SIGNAL0 -> CHANNEL0 -> EVENT0
24 * EVENT1 <- CHANNEL1 <- SIGNAL1
40 IPC_EVENT_BIT(8) | \
44 IPC_EVENT_BIT(12) | \
60 [8] = BIT(8),
64 [12] = BIT(12),
78 [8] = BIT(8),
82 [12] = BIT(12),
|
| /Zephyr-latest/drivers/spi/ |
| D | spi_andes_atcspi200.h | 4 * SPDX-License-Identifier: Apache-2.0
42 #define TFMAT_DATA_LEN_OFFSET (8)
49 #define TFMAT_DATA_LEN_MSK GENMASK(12, 8)
54 #define TCTRL_WR_TCNT_OFFSET (12)
57 #define TCTRL_WR_TCNT_MSK GENMASK(20, 12)
80 #define STAT_RX_NUM_MSK GENMASK(12, 8)
86 #define CTRL_RX_THRES_OFFSET (8)
93 #define CTRL_RX_THRES_MSK GENMASK(12, 8)
102 #define MAX_CHAIN_SIZE (8)
117 #define GET_RX_NUM(base) (RX_NUM_STAT(base) >> 8)
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| /Zephyr-latest/boards/st/stm32h7s78_dk/ |
| D | arduino_r3_connector.dtsi | 4 * SPDX-License-Identifier: Apache-2.0
9 compatible = "arduino-header-r3";
10 #gpio-cells = <2>;
11 gpio-map-mask = <0xffffffff 0xffffffc0>;
12 gpio-map-pass-thru = <0 0x3f>;
13 gpio-map = <0 0 &gpioc 0 0>, /* A0 */
16 <3 0 &gpiof 12 0>, /* A3 */
20 <7 0 &gpioe 8 0>, /* D1 */
21 <8 0 &gpiof 1 0>, /* D2 */
22 <9 0 &gpiod 12 0>, /* D3 */
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| /Zephyr-latest/dts/bindings/display/ |
| D | led-strip-matrix.yaml | 2 # SPDX-License-Identifier: Apache-2.0
7 compatible: "led-strip-matrix"
9 include: display-controller.yaml
23 [ 8][ 9][10][11]
24 [12][13][14][15]
29 [ 8][ 9][10][11]
30 [15][14][13][12]
32 start-from-right:
40 [11][10][ 9][ 8]
41 [12][13][14][15]
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| /Zephyr-latest/tests/drivers/adc/adc_api/boards/ |
| D | nucleo_wba55cg.overlay | 2 * SPDX-License-Identifier: Apache-2.0
10 io-channels = <&adc4 7>, <&adc4 8>;
15 pinctrl-0 = <&adc4_in7_pa2 &adc4_in8_pa1>;
16 #address-cells = <1>;
17 #size-cells = <0>;
23 zephyr,acquisition-time = <ADC_ACQ_TIME_MAX>;
24 zephyr,resolution = <12>;
27 channel@8 {
28 reg = <8>;
31 zephyr,acquisition-time = <ADC_ACQ_TIME_MAX>;
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| D | max32672evkit.overlay | 4 * SPDX-License-Identifier: Apache-2.0
10 io-channels = <&adc 8>, <&adc 9>;
16 pinctrl-0 = <&ain8_p0_16 &ain9_p0_17>;
17 pinctrl-names = "default";
18 #address-cells = <1>;
19 #size-cells = <0>;
21 channel@8 {
22 reg = <8>;
25 zephyr,acquisition-time = <ADC_ACQ_TIME_DEFAULT>;
26 zephyr,resolution = <12>;
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| D | max32672fthr.overlay | 4 * SPDX-License-Identifier: Apache-2.0
10 io-channels = <&adc 8>, <&adc 9>;
16 pinctrl-0 = <&ain8_p0_16 &ain9_p0_17>;
17 pinctrl-names = "default";
18 #address-cells = <1>;
19 #size-cells = <0>;
21 channel@8 {
22 reg = <8>;
25 zephyr,acquisition-time = <ADC_ACQ_TIME_DEFAULT>;
26 zephyr,resolution = <12>;
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| /Zephyr-latest/samples/drivers/adc/adc_dt/boards/ |
| D | sam_e70_xplained_same70q21.overlay | 2 * SPDX-License-Identifier: Apache-2.0
10 io-channels = <&afec0 0>, <&afec0 8>;
15 #address-cells = <1>;
16 #size-cells = <0>;
22 zephyr,acquisition-time = <ADC_ACQ_TIME_DEFAULT>;
23 zephyr,resolution = <12>;
26 channel@8 {
27 reg = <8>;
30 zephyr,acquisition-time = <ADC_ACQ_TIME_DEFAULT>;
31 zephyr,resolution = <12>;
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| D | sam_v71_xult_samv71q21.overlay | 2 * SPDX-License-Identifier: Apache-2.0
10 io-channels = <&afec0 0>, <&afec0 8>;
15 #address-cells = <1>;
16 #size-cells = <0>;
22 zephyr,acquisition-time = <ADC_ACQ_TIME_DEFAULT>;
23 zephyr,resolution = <12>;
26 channel@8 {
27 reg = <8>;
30 zephyr,acquisition-time = <ADC_ACQ_TIME_DEFAULT>;
31 zephyr,resolution = <12>;
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| /Zephyr-latest/dts/bindings/clock/ |
| D | st,stm32u5-msi-clock.yaml | 2 # SPDX-License-Identifier: Apache-2.0
6 compatible: "st,stm32u5-msi-clock"
9 - name: st,stm32-msi-clock.yaml
10 property-blocklist:
11 - msi-range
15 msi-range:
22 - 0 # range 0 around 48 MHz
23 - 1 # range 1 around 24 MHz
24 - 2 # range 2 around 16 MHz
25 - 3 # range 3 around 12 MHz
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| /Zephyr-latest/samples/tfm_integration/tfm_secure_partition/dummy_partition/ |
| D | dummy_partition.c | 4 * SPDX-License-Identifier: Apache-2.0
21 { {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15} },
22 { {1, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15} },
23 { {2, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15} },
24 { {3, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15} },
25 { {4, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15} },
77 if (msg->in_size[0] != sizeof(secret_index)) { in tfm_dp_secret_digest_ipc()
82 num = psa_read(msg->handle, 0, &secret_index, msg->in_size[0]); in tfm_dp_secret_digest_ipc()
83 if (num != msg->in_size[0]) { in tfm_dp_secret_digest_ipc()
87 return tfm_dp_secret_digest(secret_index, msg->out_size[0], in tfm_dp_secret_digest_ipc()
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