Lines Matching +full:8 +full:- +full:12
2 * Copyright (c) 2021-2023 IoT.bzh
4 * SPDX-License-Identifier: Apache-2.0
9 #include <zephyr/dt-bindings/pinctrl/renesas/pinctrl-r8a77961.h>
18 { PIN_QSPI0_IO3, 12, 2 }, /* QSPI0_IO3 */
19 { PIN_QSPI0_SSL, 8, 2 }, /* QSPI0_SSL */
29 { PIN_RPC_INT_N, 12, 2 }, /* RPC_INT# */
30 { PIN_RPC_WP_N, 8, 2 }, /* RPC_WP# */
40 { PIN_AVB_RD3, 12, 3 }, /* AVB_RD3 */
41 { PIN_AVB_TX_CTL, 8, 3 }, /* AVB_TX_CTL */
51 { PIN_AVB_MDIO, 12, 3 }, /* AVB_MDIO */
52 { RCAR_GP_PIN(2, 9), 8, 3 }, /* AVB_MDC */
58 { RCAR_GP_PIN(2, 12), 28, 3 }, /* AVB_LINK */
62 { RCAR_GP_PIN(2, 1), 12, 3 }, /* IRQ1 */
63 { RCAR_GP_PIN(2, 2), 8, 3 }, /* IRQ2 */
72 { RCAR_GP_PIN(2, 8), 16, 3 }, /* PWM2 */
73 { RCAR_GP_PIN(1, 0), 12, 3 }, /* A0 */
74 { RCAR_GP_PIN(1, 1), 8, 3 }, /* A1 */
84 { RCAR_GP_PIN(1, 8), 12, 3 }, /* A8 */
85 { RCAR_GP_PIN(1, 9), 8, 3 }, /* A9 */
91 { RCAR_GP_PIN(1, 12), 28, 3 }, /* A12 */
95 { RCAR_GP_PIN(1, 16), 12, 3 }, /* A16 */
96 { RCAR_GP_PIN(1, 17), 8, 3 }, /* A17 */
106 { RCAR_GP_PIN(1, 23), 12, 3 }, /* RD */
107 { RCAR_GP_PIN(1, 24), 8, 3 }, /* RD_WR */
117 { RCAR_GP_PIN(0, 2), 12, 3 }, /* D2 */
118 { RCAR_GP_PIN(0, 3), 8, 3 }, /* D3 */
126 { RCAR_GP_PIN(0, 8), 20, 3 }, /* D8 */
128 { RCAR_GP_PIN(0, 10), 12, 3 }, /* D10 */
129 { RCAR_GP_PIN(0, 11), 8, 3 }, /* D11 */
130 { RCAR_GP_PIN(0, 12), 4, 3 }, /* D12 */
139 { RCAR_GP_PIN(7, 2), 12, 3 }, /* GP7_02 */
140 { RCAR_GP_PIN(7, 3), 8, 3 }, /* GP7_03 */
157 { RCAR_GP_PIN(3, 2), 12, 3 }, /* SD0_DAT0 */
158 { RCAR_GP_PIN(3, 3), 8, 3 }, /* SD0_DAT1 */
166 { RCAR_GP_PIN(3, 8), 20, 3 }, /* SD1_DAT0 */
168 { RCAR_GP_PIN(3, 10), 12, 3 }, /* SD1_DAT2 */
169 { RCAR_GP_PIN(3, 11), 8, 3 }, /* SD1_DAT3 */
179 { RCAR_GP_PIN(4, 6), 12, 3 }, /* SD2_DS */
180 { RCAR_GP_PIN(4, 7), 8, 3 }, /* SD3_CLK */
181 { RCAR_GP_PIN(4, 8), 4, 3 }, /* SD3_CMD */
188 { RCAR_GP_PIN(4, 12), 20, 3 }, /* SD3_DAT3 */
190 { RCAR_GP_PIN(4, 14), 12, 3 }, /* SD3_DAT5 */
191 { RCAR_GP_PIN(4, 15), 8, 3 }, /* SD3_DAT6 */
197 { RCAR_GP_PIN(3, 12), 28, 3 }, /* SD0_CD */
201 { RCAR_GP_PIN(5, 0), 12, 3 }, /* SCK0 */
202 { RCAR_GP_PIN(5, 1), 8, 3 }, /* RX0 */
212 { RCAR_GP_PIN(5, 8), 12, 3 }, /* RTS1 */
213 { RCAR_GP_PIN(5, 9), 8, 3 }, /* SCK2 */
219 { RCAR_GP_PIN(5, 12), 28, 3 }, /* HSCK0 */
223 { RCAR_GP_PIN(5, 16), 12, 3 }, /* HRTS0 */
224 { RCAR_GP_PIN(5, 17), 8, 3 }, /* MSIOF0_SCK */
234 { RCAR_GP_PIN(5, 24), 12, 3 }, /* MLB_SIG */
235 { RCAR_GP_PIN(5, 25), 8, 3 }, /* MLB_DAT */
245 { RCAR_GP_PIN(6, 5), 12, 3 }, /* SSI_SCK349 */
246 { RCAR_GP_PIN(6, 6), 8, 3 }, /* SSI_WS349 */
248 { RCAR_GP_PIN(6, 8), 0, 3 }, /* SSI_SCK4 */
255 { RCAR_GP_PIN(6, 12), 16, 3 }, /* SSI_WS5 */
256 { RCAR_GP_PIN(6, 13), 12, 3 }, /* SSI_SDATA5 */
257 { RCAR_GP_PIN(6, 14), 8, 3 }, /* SSI_SCK6 */
267 { RCAR_GP_PIN(6, 21), 12, 3 }, /* SSI_SDATA9 */
268 { RCAR_GP_PIN(6, 22), 8, 3 }, /* AUDIO_CLKA */
278 { RCAR_GP_PIN(6, 29), 12, 3 }, /* USB30_OVC */
279 { RCAR_GP_PIN(6, 30), 8, 3 }, /* GP6_30/USB2_CH3_PWEN */
300 [8] = PIN_QSPI1_MISO_IO1, /* QSPI1_MISO_IO1 */
304 [12] = PIN_RPC_INT_N, /* RPC_INT# */
326 [0] = RCAR_GP_PIN(2, 12), /* AVB_LINK */
334 [8] = RCAR_GP_PIN(2, 5), /* IRQ5 */
337 [11] = RCAR_GP_PIN(2, 8), /* PWM2_A */
338 [12] = RCAR_GP_PIN(1, 0), /* A0 */
346 [20] = RCAR_GP_PIN(1, 8), /* A8 */
350 [24] = RCAR_GP_PIN(1, 12), /* A12 */
368 [8] = RCAR_GP_PIN(1, 27), /* EX_WAIT0_A */
372 [12] = RCAR_GP_PIN(0, 2), /* D2 */
378 [18] = RCAR_GP_PIN(0, 8), /* D8 */
382 [22] = RCAR_GP_PIN(0, 12), /* D12 */
402 [8] = PIN_NONE,
406 [12] = RCAR_GP_PIN(3, 2), /* SD0_DAT0 */
412 [18] = RCAR_GP_PIN(3, 8), /* SD1_DAT0 */
424 [30] = RCAR_GP_PIN(4, 8), /* SD3_CMD */
430 [2] = RCAR_GP_PIN(4, 12), /* SD3_DAT3 */
436 [8] = RCAR_GP_PIN(3, 12), /* SD0_CD */
440 [12] = RCAR_GP_PIN(5, 0), /* SCK0 */
448 [20] = RCAR_GP_PIN(5, 8), /* RTS1_N */
452 [24] = RCAR_GP_PIN(5, 12), /* HSCK0 */
470 [8] = RCAR_GP_PIN(6, 1), /* SSI_WS01239 */
474 [12] = RCAR_GP_PIN(6, 5), /* SSI_SCK349 */
477 [15] = RCAR_GP_PIN(6, 8), /* SSI_SCK4 */
481 [19] = RCAR_GP_PIN(6, 12), /* SSI_WS5 */
504 [8] = PIN_NONE,
508 [12] = PIN_NONE,