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/Zephyr-latest/soc/espressif/esp32s3/
DKconfig24 If you use 16KB instruction cache rather than 32KB instruction cache,
25 then the other 16KB will be managed by heap allocator.
28 bool "16KB"
30 bool "32KB"
85 If you use 32KB data cache rather than 64KB data cache,
86 the other 32KB will be added to the heap.
89 bool "16KB"
91 bool "32KB"
93 bool "64KB"
98 # For 16KB the actual configuration is 32kb cache, but 16kb will be reserved for heap at startup
[all …]
/Zephyr-latest/soc/nxp/kinetis/k6x/
DREADME.txt3 Although the K64F CPU has 64 kB of SRAM at 0x1FFF0000 (code space), it is not
4 used by the FSL FRDM K64F platform. Only the 192 kB region based at the
10 CONFIG_SRAM_SIZE=64 # Measured in kB
/Zephyr-latest/drivers/flash/
Dflash_gd32_v3.c25 {.pages_count = 4, .pages_size = KB(16)},
26 {.pages_count = 1, .pages_size = KB(64)},
27 {.pages_count = 3, .pages_size = KB(128)},
31 {.pages_count = 4, .pages_size = KB(16)},
32 {.pages_count = 1, .pages_size = KB(64)},
33 {.pages_count = 7, .pages_size = KB(128)},
37 {.pages_count = 4, .pages_size = KB(16)},
38 {.pages_count = 1, .pages_size = KB(64)},
39 {.pages_count = 7, .pages_size = KB(128)},
40 {.pages_count = 4, .pages_size = KB(16)},
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Dflash_stm32f4x.c328 * sectors (16 KB) in the second bank occurring after the large ones
329 * (128 KB) in the first. We could consider supporting this as two
338 {.pages_count = 4, .pages_size = KB(16)},
339 {.pages_count = 1, .pages_size = KB(64)},
344 {.pages_count = 4, .pages_size = KB(16)},
345 {.pages_count = 1, .pages_size = KB(64)},
346 {.pages_count = 1, .pages_size = KB(128)},
355 {.pages_count = 4, .pages_size = KB(16)},
356 {.pages_count = 1, .pages_size = KB(64)},
357 {.pages_count = 3, .pages_size = KB(128)},
[all …]
Dflash_stm32f7x.c229 {.pages_count = 2, .pages_size = KB(32)},
234 {.pages_count = 4, .pages_size = KB(16)},
240 {.pages_count = 4, .pages_size = KB(16)},
241 {.pages_count = 1, .pages_size = KB(64)},
242 {.pages_count = 3, .pages_size = KB(128)},
247 {.pages_count = 4, .pages_size = KB(32)},
248 {.pages_count = 1, .pages_size = KB(128)},
249 {.pages_count = 3, .pages_size = KB(256)},
255 {.pages_count = 4, .pages_size = KB(32)},
256 {.pages_count = 1, .pages_size = KB(128)},
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/Zephyr-latest/dts/arm/nxp/
Dnxp_kv5xf1m0vlx24.dtsi11 /* 64KB ITCM @ 0, 128KB DTCM @ 20000000, 64KB OCRAM @ 2F000000 */
Dnxp_kv5xf512vlx24.dtsi11 /* 64KB ITCM @ 0, 64KB DTCM @ 20000000 */
15 reg = <0x20000000 DT_SIZE_K(64)>;
Dnxp_rt1024.dtsi19 * ITCM: 64KB
20 * DTCM: 64KB
21 * OCRAM: 128KB
24 reg = <0x00000000 DT_SIZE_K(64)>;
28 reg = <0x20000000 DT_SIZE_K(64)>;
/Zephyr-latest/dts/common/nordic/
Dnrf5340_cpuapp_partition.dtsi14 * 0x0000_0000 BL2 - MCUBoot (64 KB)
15 * 0x0001_0000 Primary image area (448 KB):
16 * 0x0001_0000 Secure image primary (256 KB)
17 * 0x0005_0000 Non-secure image primary (192 KB)
18 * 0x0008_0000 Secondary image area (448 KB):
19 * 0x0008_0000 Secure image secondary (256 KB)
20 * 0x000c_0000 Non-secure image secondary (192 KB)
21 * 0x000f_0000 Protected Storage Area (16 KB)
22 * 0x000f_4000 Internal Trusted Storage Area (8 KB)
23 * 0x000f_6000 OTP / NV counters area (8 KB)
[all …]
Dnrf5340_shared_sram_partition.dtsi16 * By default the last 64 kB of application core SRAM is allocated as shared
31 /* Last 64 kB of sram0 */
Dnrf91xx_partition.dtsi14 * 0x0000_0000 BL2 - MCUBoot (64 KB)
15 * 0x0001_0000 Primary image area (448 KB):
16 * 0x0001_0000 Secure image primary (256 KB)
17 * 0x0005_0000 Non-secure image primary (192 KB)
18 * 0x0008_0000 Secondary image area (448 KB):
19 * 0x0008_0000 Secure image secondary (256 KB)
20 * 0x000c_0000 Non-secure image secondary (192 KB)
21 * 0x000f_0000 Protected Storage Area (16 KB)
22 * 0x000f_4000 Internal Trusted Storage Area (8 KB)
23 * 0x000f_6000 OTP / NV counters area (8 KB)
[all …]
/Zephyr-latest/dts/arm/st/f7/
Dstm32f722.dtsi10 /* 16KB ITCM @ 0x0, 64KB DTCM @ 0x20000000,
11 * 176KB SRAM1 @ 0x20010000, 16KB SRAM2 @ 0x2003C00
22 reg = <0x20000000 DT_SIZE_K(64)>;
Dstm32f745.dtsi10 /* 64KB DTCM @ 20000000, 240KB SRAM1 @ 20010000, 16KB SRAM2 @ 2004C000 */
20 reg = <0x20000000 DT_SIZE_K(64)>;
72 interrupts = <63 0>, <64 0>, <65 0>, <66 0>;
/Zephyr-latest/boards/seagate/legend/
Dlegend.dts103 * Total size : 256 KB
104 * Erase size : whole chip, 64 and 32 KB blocks, 4 KB sectors,
115 * Total size : 128 KB
116 * Erase size : whole chip, 64 and 32 KB blocks, 4 KB sectors
126 * Total size : 64 KB
127 * Erase size : whole chip, 64 and 32 KB blocks, 4 KB sectors
/Zephyr-latest/dts/arm/renesas/ra/ra6/
Dr7fa6e10f2cfp.dtsi13 block-32kb-linear-end = <37>;
14 block-32kb-dual-low-end = <21>;
15 block-32kb-dual-high-end = <91>;
28 erase-block-size = <64>;
Dr7fa6m4af3cfb.dtsi13 block-32kb-linear-end = <37>;
14 block-32kb-dual-low-end = <21>;
15 block-32kb-dual-high-end = <91>;
28 erase-block-size = <64>;
Dr7fa6m5bh3cfc.dtsi13 block-32kb-linear-end = <69>;
14 block-32kb-dual-low-end = <37>;
15 block-32kb-dual-high-end = <107>;
28 erase-block-size = <64>;
Dr7fa6m3ah3cfc.dtsi12 block-32kb-linear-end = <69>;
23 reg = <0x40100000 DT_SIZE_K(64)>;
25 erase-block-size = <64>;
/Zephyr-latest/drivers/sdhc/
DKconfig.sdhc_cdns14 # Cadence SDHC DMA needs 64 bit aligned buffers
24 configure this flag if they require to transfer more than 8*64Kb of data.
/Zephyr-latest/samples/bluetooth/hci_ipc/
Doverlay-nrf5340_cpunet_iso_nrf21540_ek-bt_ll_sw_split.conf2 # to be able to fit in 64KB RAM, in case needed in the future.
/Zephyr-latest/boards/beagle/beaglebone_ai64/doc/
Dindex.rst6 BeagleBone AI-64 is a computational platform powered by TI J721E SoC, which is
12 BeagleBone AI-64 is powered by TI J721E SoC, which has three domains (MAIN,
19 * 16 KB instruction cache.
20 * 16 KB data cache.
21 * 64 KB TCM.
79 | ATCM | 0x05c00000 | 0x05d00000 | 0x05e00000 | 0x05f00000 | 32KB |
81 | BTCM | 0x05c10000 | 0x05d10000 | 0x05e10000 | 0x05f00000 | 32KB |
92 targeting one of the Cortex R5F on BeagleBone AI-64:
116 Zephyr on BeagleBone AI-64 J721E Cortex R5 uses UART 2 (Rx p8.22, Tx p8.34)
122 * `BeagleBone AI-64 Homepage <https://www.beagleboard.org/boards/beaglebone-ai-64>`_
/Zephyr-latest/boards/ezurio/bl5340_dvk/
Dbl5340_dvk_nrf5340_cpuapp_partition_conf.dtsi43 * - Lowest 256 kB SRAM allocated to Secure image (sram0_s)
44 * - Middle 192 kB allocated to Non-Secure image (sram0_ns)
45 * - Upper 64 kB SRAM allocated as Shared memory (sram0_shared)
/Zephyr-latest/boards/waveshare/open103z/support/
Dopenocd.cfg3 # Work-area size (RAM size) = 64KB
/Zephyr-latest/dts/bindings/interrupt-controller/
Darm,gic-v3.yaml23 redistributor-stride = <0x40000>; /* 256kB stride */
43 memory. Must be a multiple of 64kB. Required if the distance between
44 redistributors is not the default 128kB.
/Zephyr-latest/drivers/cache/
Dcache_aspeed.c12 * cache area control: each bit controls 32KB cache area
16 * bit[0]: 1st 32KB from 0x0000_0000 to 0x0000_7fff
17 * bit[1]: 2nd 32KB from 0x0000_8000 to 0x0000_ffff
19 * bit[22]: 23th 32KB from 0x000a_8000 to 0x000a_ffff
20 * bit[23]: 24th 32KB from 0x000b_0000 to 0x000b_ffff
27 #define CACHED_SRAM_SIZE KB(CONFIG_SRAM_SIZE)
40 /* cache size = 32B * 128 = 4KB */
82 * addr = 0x100 (cacheline aligned), size = 64
83 * then head = 0x100, number of cache line to be invalidated = 64 / 32 = 2
87 * addr = 0x104 (cacheline unaligned), size = 64
[all …]

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