1/*
2 * Copyright (c) 2020 Kwon Tae-young <tykwon@m2i.co.kr>
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7#include <st/f7/stm32f7.dtsi>
8
9/ {
10	/* 64KB DTCM @ 20000000, 240KB SRAM1 @ 20010000, 16KB SRAM2 @ 2004C000 */
11
12	sram0: memory@20010000 {
13		compatible = "zephyr,memory-region", "mmio-sram";
14		reg = <0x20010000 DT_SIZE_K(256)>;
15		zephyr,memory-region = "SRAM0";
16	};
17
18	dtcm: memory@20000000 {
19		compatible = "zephyr,memory-region", "arm,dtcm";
20		reg = <0x20000000 DT_SIZE_K(64)>;
21		zephyr,memory-region = "DTCM";
22	};
23
24	soc {
25		compatible = "st,stm32f745", "st,stm32f7", "simple-bus";
26
27		pinctrl: pin-controller@40020000 {
28			reg = <0x40020000 0x2C00>;
29
30			gpioj: gpio@40022400 {
31				compatible = "st,stm32-gpio";
32				gpio-controller;
33				#gpio-cells = <2>;
34				reg = <0x40022400 0x400>;
35				clocks = <&rcc STM32_CLOCK(AHB1, 9U)>;
36			};
37
38			gpiok: gpio@40022800 {
39				compatible = "st,stm32-gpio";
40				gpio-controller;
41				#gpio-cells = <2>;
42				reg = <0x40022800 0x400>;
43				clocks = <&rcc STM32_CLOCK(AHB1, 10U)>;
44			};
45		};
46
47		i2c4: i2c@40006000 {
48			compatible = "st,stm32-i2c-v2";
49			clock-frequency = <I2C_BITRATE_STANDARD>;
50			#address-cells = <1>;
51			#size-cells = <0>;
52			reg = <0x40006000 0x400>;
53			clocks = <&rcc STM32_CLOCK(APB1, 24U)>;
54			interrupts = <95 0>, <96 0>;
55			interrupt-names = "event", "error";
56			status = "disabled";
57		};
58
59		spi6: spi@40015400 {
60			compatible = "st,stm32-spi-fifo", "st,stm32-spi";
61			#address-cells = <1>;
62			#size-cells = <0>;
63			reg = <0x40015400 0x400>;
64			clocks = <&rcc STM32_CLOCK(APB2, 21U)>;
65			interrupts = <86 5>;
66			status = "disabled";
67		};
68
69		can2: can@40006800 {
70			compatible = "st,stm32-bxcan";
71			reg = <0x40006800 0x400>;
72			interrupts = <63 0>, <64 0>, <65 0>, <66 0>;
73			interrupt-names = "TX", "RX0", "RX1", "SCE";
74			clocks = <&rcc STM32_CLOCK(APB1, 26U)>;
75			status = "disabled";
76		};
77
78		mac: ethernet@40028000 {
79			compatible = "st,stm32-ethernet";
80			reg = <0x40028000 0x8000>;
81			interrupts = <61 0>;
82			clock-names = "stmmaceth", "mac-clk-tx",
83				      "mac-clk-rx", "mac-clk-ptp";
84			clocks = <&rcc STM32_CLOCK(AHB1, 25U)>,
85				 <&rcc STM32_CLOCK(AHB1, 26U)>,
86				 <&rcc STM32_CLOCK(AHB1, 27U)>,
87				 <&rcc STM32_CLOCK(AHB1, 28U)>;
88			status = "disabled";
89		};
90	};
91
92	smbus4: smbus4 {
93		compatible = "st,stm32-smbus";
94		#address-cells = <1>;
95		#size-cells = <0>;
96		i2c = <&i2c4>;
97		status = "disabled";
98	};
99};
100