| /Zephyr-latest/dts/bindings/clock/ |
| D | st,stm32c0-hsi-clock.yaml | 6 On STM32C0, HSI is a 48MHz fixed clock.
12 - 1 ==> HSISYS = 48MHZ
13 - 2 ==> HSISYS = 24MHZ
14 - 4 ==> HSISYS = 12MHZ
15 - 8 ==> HSISYS = 6MHZ
16 - 16 ==> HSISYS = 3MHZ
17 - 32 ==> HSISYS = 1.5MHz
18 - 64 ==> HSISYS = 0.75MHZ
19 - 128 ==> HSISYS = 0.375MHz
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| D | st,stm32l0-pll-clock.yaml | 8 input frequency from 2 to 24 MHz.
16 The PLL output frequency must not exceed 32 MHz.
45 - 96 MHz when the product is in Range 1
46 - 48 MHz when the product is in Range 2
47 - 24 MHz when the product is in Range 3
49 programmed to output a 96 MHz frequency (USBCLK = PLLVCO/2).
59 - 48
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| D | microchip,xec-pcr.yaml | 17 description: Divide 96 MHz PLL clock to produce Cortex-M4 core clock
22 PWM and TACH clock domain divided down from 48 MHz AHB clock. The
43 32KHz clock monitor minimum valid 32KHz period in 48MHz units
49 32KHz clock monitor maximum valid 32KHz period in 48MHz units
55 Maximum duty cycle variation. Difference in units of 48HMz between
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| D | st,stm32u5-msi-clock.yaml | 22 - 0 # range 0 around 48 MHz
23 - 1 # range 1 around 24 MHz
24 - 2 # range 2 around 16 MHz
25 - 3 # range 3 around 12 MHz
26 - 4 # range 4 around 4 MHz (reset value)
27 - 5 # range 5 around 2 MHz
28 - 6 # range 6 around 1.33 MHz
29 - 7 # range 7 around 1 MHz
30 - 8 # range 8 around 3.072 MHz
31 - 9 # range 9 around 1.536 MHz
[all …]
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| D | st,stm32-msi-clock.yaml | 23 - 5 # range 5 around 2 MHz
24 - 6 # range 6 around 4 MHz (reset value)
25 - 7 # range 7 around 8 MHz
26 - 8 # range 8 around 16 MHz
27 - 9 # range 9 around 24 MHz
28 - 10 # range 10 around 32 MHz
29 - 11 # range 11 around 48 MHz
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| D | nuvoton,numaker-scc.yaml | 17 Enable/disable 4~24 MHz external crystal oscillator (HXT)
35 Enable/disable 48 MHz high-speed internal RC oscillator (HIRC48)
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| D | st,stm32f1-pll-clock.yaml | 14 The PLL output frequency must not exceed 72 MHz.
43 Optional PLL output divisor to generate a 48MHz USB clock.
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| /Zephyr-latest/soc/ene/kb1200/ |
| D | soc.c | 31 /* AHB/APB clock select 96MHz/48MHz */ in clock_init()
34 /* AHB/APB clock select 48MHz/24MHz */ in clock_init()
37 /* AHB/APB clock select 24MHz/12MHz */ in clock_init()
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| /Zephyr-latest/soc/sifive/sifive_freedom/fe300/ |
| D | clock.c | 20 * HFXOSC (16 MHz) is used to produce coreclk (and therefore tlclk / in soc_early_init_hook()
22 * - 16 MHz (bypass HFPLL). in soc_early_init_hook()
23 * - 48 MHz - 320 MHz, in 8 MHz steps (use HFPLL). in soc_early_init_hook()
25 BUILD_ASSERT(MHZ(16) == CORECLK_HZ || in soc_early_init_hook()
26 (MHZ(48) <= CORECLK_HZ && MHZ(320) >= CORECLK_HZ && in soc_early_init_hook()
27 (CORECLK_HZ % MHZ(8)) == 0), in soc_early_init_hook()
32 if (MHZ(16) == CORECLK_HZ) { in soc_early_init_hook()
36 /* refr = 8 MHz. */ in soc_early_init_hook()
40 /* Select Q divisor to produce vco on [384 MHz, 768 MHz]. */ in soc_early_init_hook()
41 if (MHZ(768) / 8 >= CORECLK_HZ) { in soc_early_init_hook()
[all …]
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| /Zephyr-latest/soc/ite/ec/it8xxx2/ |
| D | soc.c | 55 pllfreq = MHZ(8); in chip_get_pll_freq()
58 pllfreq = MHZ(16); in chip_get_pll_freq()
61 pllfreq = MHZ(24); in chip_get_pll_freq()
64 pllfreq = MHZ(32); in chip_get_pll_freq()
67 pllfreq = MHZ(48); in chip_get_pll_freq()
70 pllfreq = MHZ(64); in chip_get_pll_freq()
73 pllfreq = MHZ(72); in chip_get_pll_freq()
76 pllfreq = MHZ(96); in chip_get_pll_freq()
121 * PLL frequency setting = 4 (48MHz)
122 * MCU div = 0 (PLL / 1 = 48 mhz)
[all …]
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| D | Kconfig | 105 bool "Flash frequency is 48MHz"
109 Change frequency of PLL, CPU, and flash to 48MHz during initialization.
112 (PLL and CPU run at 48MHz, flash frequency is 16MHz)
140 bool "EC bus is 24MHz"
142 Raise EC bus to 24MHz (default is 8MHz).
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| /Zephyr-latest/soc/atmel/sam0/common/ |
| D | soc_saml2x.c | 22 * the CPU clock will be configured to 48 MHz, and run via DFLL48M.
26 * GCLK Gen 0 -> GCLK_MAIN @ 48 Mhz
28 * GCLK Gen 2 -> USB @ 48 MHz
29 * GCLK Gen 3 -> ADC @ 24 MHz (further /2 in the ADC peripheral)
34 /* by default, OSC16M will be enabled at 4 MHz, and the CPU will in gclk_reset()
140 /* if the target frequency is 48 MHz, then the calibration value can be used to in dfll48m_init()
171 /* use a 32.768 kHz reference ... 48e6 / 32,768 = 1,464.843... */ in dfll48m_init()
174 /* use a 16 MHz -> 31.25 kHz reference... 48e6 / 31,250 = 1,536 in dfll48m_init()
176 * 16 MHz source directly in dfll48m_init()
198 /* PL2, >= 2.7v, 48MHz = 2 wait states */ in flash_waitstates_init()
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| /Zephyr-latest/soc/microchip/mec/mec15xx/ |
| D | power.c | 19 * Lower power dissipation, 48MHz PLL is off
22 * between 16 to 25 MHz. Minimum 3ms until PLL reaches lock
23 * frequency of 48MHz.
34 * possibly polling the DUT then MEC1501 will not shut off its 48MHz
85 * Higher power dissipation, 48MHz PLL remains on.
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| /Zephyr-latest/samples/boards/ti/cc13x2_cc26x2/system_off/src/ |
| D | ext_flash.c | 42 * 3 cycles per loop: 8 loops @ 48 Mhz = 0.5 us. in CC1352R1_LAUNCHXL_sendExtFlashByte()
52 * 3 cycles per loop: 700 loops @ 48 Mhz ~= 44 us in CC1352R1_LAUNCHXL_sendExtFlashByte()
69 /* 3 cycles per loop: 1 loop @ 48 Mhz ~= 62 ns */ in CC1352R1_LAUNCHXL_wakeUpExtFlash()
72 /* 3 cycles per loop: 560 loops @ 48 Mhz ~= 35 us */ in CC1352R1_LAUNCHXL_wakeUpExtFlash()
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| /Zephyr-latest/soc/microchip/mec/ |
| D | Kconfig | 37 bool "SPI flash clock rate of 12 MHz"
40 bool "SPI flash clock rate of 16 MHz"
43 bool "SPI flash clock rate of 24 MHz"
46 bool "SPI flash clock rate of 48 MHz"
55 default 48 if MCHP_MEC_HEADER_SPI_FREQ_MHZ_48
65 bool "SPI flash operates full-duplex with frequency (< 25 MHz)"
265 range 1 48
268 and main 96 MHz clock (MCK):
270 Allowed divider values: 1, 3, 4, 16, and 48.
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| /Zephyr-latest/dts/bindings/pwm/ |
| D | microchip,xec-pwmbbled.yaml | 51 - Main system clock (48MHz)
53 When BBLED enter into Suspend state, 48MHz clock will be switched off by
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| /Zephyr-latest/dts/bindings/rng/ |
| D | st,stm32-rng.yaml | 22 In the provided example, MSI should be configured to provide 48Mhz clock.
29 to certify NIST SP800-90B. RNG clock source must be 48MHz.
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| /Zephyr-latest/drivers/watchdog/ |
| D | Kconfig.cc13xx_cc26xx | 20 E.g., for the standard 48 MHz MCU clock, the following:
21 0xFFFFFFFF / (48^9 / 32 / 1000) [ms]
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| /Zephyr-latest/drivers/disk/ |
| D | Kconfig.sdmmc | 66 bool "Runtime SDMMC 48MHz clock check"
70 Enable SDMMC clock 48MHz configuration runtime check.
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| /Zephyr-latest/soc/microchip/mec/mec172x/ |
| D | power.c | 27 * Lower power dissipation, 48MHz PLL is off
30 * between 16 to 25 MHz. Minimum 3ms until PLL reaches lock
31 * frequency of 48MHz.
42 * possibly polling the DUT then MEC1501 will not shut off its 48MHz
117 * Higher power dissipation, 48MHz PLL remains on.
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| /Zephyr-latest/boards/shields/x_nucleo_iks02a1/boards/ |
| D | nucleo_f411re.overlay | 13 status = "okay"; /* 48MHz on PLLI2SQ */
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| /Zephyr-latest/soc/nxp/kinetis/kl2x/ |
| D | soc.c | 30 * Core clock: 48MHz in clock_init()
31 * Bus clock: 24MHz in clock_init()
84 /* Initialize system clock to 48 MHz */ in soc_early_init_hook()
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| /Zephyr-latest/soc/telink/tlsr/tlsr951x/ |
| D | soc.c | 24 /* Define 48 MHz and 96 MHz CCLK clock options (not present in HAL) */
66 #error "Unsupported clock-frequency. Supported values: 16, 24, 32, 48, 64 and 96 MHz"
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| /Zephyr-latest/tests/drivers/clock_control/stm32_clock_configuration/stm32_common_devices/src/ |
| D | test_stm32_clock_configuration_sdmmc.c | 20 #warning "Missing clock 48MHz"
48 /* CLK 48 is enabled through the clock-mux */ in ZTEST()
49 zassert_true(DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(clk48)), "No clock 48MHz"); in ZTEST()
68 "Expected SDMMC src: CLK 48 (0x%lx). Actual src: 0x%x", in ZTEST()
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| /Zephyr-latest/drivers/timer/ |
| D | Kconfig.mec5 | 15 full power and deep sleep. Basic timer 5 is a 48 MHz based
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