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/Zephyr-latest/dts/bindings/clock/
Dst,stm32c0-hsi-clock.yaml7 On STM32C0, HSI is a 48MHz fixed clock.
13 - 1 ==> HSISYS = 48MHZ
14 - 2 ==> HSISYS = 24MHZ
15 - 4 ==> HSISYS = 12MHZ
16 - 8 ==> HSISYS = 6MHZ
17 - 16 ==> HSISYS = 3MHZ
18 - 32 ==> HSISYS = 1.5MHz
19 - 64 ==> HSISYS = 0.75MHZ
20 - 128 ==> HSISYS = 0.375MHz
Dst,stm32l0-pll-clock.yaml8 input frequency from 2 to 24 MHz.
16 The PLL output frequency must not exceed 32 MHz.
45 - 96 MHz when the product is in Range 1
46 - 48 MHz when the product is in Range 2
47 - 24 MHz when the product is in Range 3
49 programmed to output a 96 MHz frequency (USBCLK = PLLVCO/2).
59 - 48
Dmicrochip,xec-pcr.yaml17 description: Divide 96 MHz PLL clock to produce Cortex-M4 core clock
22 PWM and TACH clock domain divided down from 48 MHz AHB clock. The
43 32KHz clock monitor minimum valid 32KHz period in 48MHz units
49 32KHz clock monitor maximum valid 32KHz period in 48MHz units
55 Maximum duty cycle variation. Difference in units of 48HMz between
Dst,stm32u5-msi-clock.yaml22 - 0 # range 0 around 48 MHz
23 - 1 # range 1 around 24 MHz
24 - 2 # range 2 around 16 MHz
25 - 3 # range 3 around 12 MHz
26 - 4 # range 4 around 4 MHz (reset value)
27 - 5 # range 5 around 2 MHz
28 - 6 # range 6 around 1.33 MHz
29 - 7 # range 7 around 1 MHz
30 - 8 # range 8 around 3.072 MHz
31 - 9 # range 9 around 1.536 MHz
[all …]
Dst,stm32-msi-clock.yaml23 - 5 # range 5 around 2 MHz
24 - 6 # range 6 around 4 MHz (reset value)
25 - 7 # range 7 around 8 MHz
26 - 8 # range 8 around 16 MHz
27 - 9 # range 9 around 24 MHz
28 - 10 # range 10 around 32 MHz
29 - 11 # range 11 around 48 MHz
/Zephyr-latest/soc/ene/kb1200/
Dsoc.c31 /* AHB/APB clock select 96MHz/48MHz */ in clock_init()
34 /* AHB/APB clock select 48MHz/24MHz */ in clock_init()
37 /* AHB/APB clock select 24MHz/12MHz */ in clock_init()
/Zephyr-latest/soc/sifive/sifive_freedom/fe300/
Dclock.c20 * HFXOSC (16 MHz) is used to produce coreclk (and therefore tlclk / in soc_early_init_hook()
22 * - 16 MHz (bypass HFPLL). in soc_early_init_hook()
23 * - 48 MHz - 320 MHz, in 8 MHz steps (use HFPLL). in soc_early_init_hook()
25 BUILD_ASSERT(MHZ(16) == CORECLK_HZ || in soc_early_init_hook()
26 (MHZ(48) <= CORECLK_HZ && MHZ(320) >= CORECLK_HZ && in soc_early_init_hook()
27 (CORECLK_HZ % MHZ(8)) == 0), in soc_early_init_hook()
32 if (MHZ(16) == CORECLK_HZ) { in soc_early_init_hook()
36 /* refr = 8 MHz. */ in soc_early_init_hook()
40 /* Select Q divisor to produce vco on [384 MHz, 768 MHz]. */ in soc_early_init_hook()
41 if (MHZ(768) / 8 >= CORECLK_HZ) { in soc_early_init_hook()
[all …]
/Zephyr-latest/soc/ite/ec/it8xxx2/
Dsoc.c55 pllfreq = MHZ(8); in chip_get_pll_freq()
58 pllfreq = MHZ(16); in chip_get_pll_freq()
61 pllfreq = MHZ(24); in chip_get_pll_freq()
64 pllfreq = MHZ(32); in chip_get_pll_freq()
67 pllfreq = MHZ(48); in chip_get_pll_freq()
70 pllfreq = MHZ(64); in chip_get_pll_freq()
73 pllfreq = MHZ(72); in chip_get_pll_freq()
76 pllfreq = MHZ(96); in chip_get_pll_freq()
121 * PLL frequency setting = 4 (48MHz)
122 * MCU div = 0 (PLL / 1 = 48 mhz)
[all …]
DKconfig105 bool "Flash frequency is 48MHz"
109 Change frequency of PLL, CPU, and flash to 48MHz during initialization.
112 (PLL and CPU run at 48MHz, flash frequency is 16MHz)
140 bool "EC bus is 24MHz"
142 Raise EC bus to 24MHz (default is 8MHz).
/Zephyr-latest/soc/atmel/sam0/common/
Dsoc_saml2x.c24 * the CPU clock will be configured to 48 MHz, and run via DFLL48M.
28 * GCLK Gen 0 -> GCLK_MAIN @ 48 Mhz
30 * GCLK Gen 2 -> USB @ 48 MHz
31 * GCLK Gen 3 -> ADC @ 24 MHz (further /2 in the ADC peripheral)
37 /* by default, OSC16M will be enabled at 4 MHz, and the CPU will in gclk_reset()
145 /* if the target frequency is 48 MHz, then the calibration value can be used to in dfll48m_init()
176 /* use a 32.768 kHz reference ... 48e6 / 32,768 = 1,464.843... */ in dfll48m_init()
179 /* use a 16 MHz -> 31.25 kHz reference... 48e6 / 31,250 = 1,536 in dfll48m_init()
181 * 16 MHz source directly in dfll48m_init()
203 /* PL2, >= 2.7v, 48MHz = 2 wait states */ in flash_waitstates_init()
/Zephyr-latest/drivers/usb/udc/
DKconfig.stm3239 bool "Runtime USB 48MHz clock check"
42 Enable USB clock 48MHz configuration runtime check.
/Zephyr-latest/soc/microchip/mec/mec15xx/
Dpower.c19 * Lower power dissipation, 48MHz PLL is off
22 * between 16 to 25 MHz. Minimum 3ms until PLL reaches lock
23 * frequency of 48MHz.
34 * possibly polling the DUT then MEC1501 will not shut off its 48MHz
85 * Higher power dissipation, 48MHz PLL remains on.
/Zephyr-latest/samples/boards/ti/cc13x2_cc26x2/system_off/src/
Dext_flash.c42 * 3 cycles per loop: 8 loops @ 48 Mhz = 0.5 us. in CC1352R1_LAUNCHXL_sendExtFlashByte()
52 * 3 cycles per loop: 700 loops @ 48 Mhz ~= 44 us in CC1352R1_LAUNCHXL_sendExtFlashByte()
69 /* 3 cycles per loop: 1 loop @ 48 Mhz ~= 62 ns */ in CC1352R1_LAUNCHXL_wakeUpExtFlash()
72 /* 3 cycles per loop: 560 loops @ 48 Mhz ~= 35 us */ in CC1352R1_LAUNCHXL_wakeUpExtFlash()
/Zephyr-latest/dts/bindings/rng/
Dst,stm32-rng.yaml22 In the provided example, MSI should be configured to provide 48Mhz clock.
29 to certify NIST SP800-90B. RNG clock source must be 48MHz.
/Zephyr-latest/dts/bindings/pwm/
Dmicrochip,xec-pwmbbled.yaml51 - Main system clock (48MHz)
53 When BBLED enter into Suspend state, 48MHz clock will be switched off by
/Zephyr-latest/soc/microchip/mec/
DKconfig37 bool "SPI flash clock rate of 12 MHz"
40 bool "SPI flash clock rate of 16 MHz"
43 bool "SPI flash clock rate of 24 MHz"
46 bool "SPI flash clock rate of 48 MHz"
55 default 48 if MCHP_MEC_HEADER_SPI_FREQ_MHZ_48
65 bool "SPI flash operates full-duplex with frequency (< 25 MHz)"
265 range 1 48
268 and main 96 MHz clock (MCK):
270 Allowed divider values: 1, 3, 4, 16, and 48.
/Zephyr-latest/drivers/watchdog/
DKconfig.cc13xx_cc26xx20 E.g., for the standard 48 MHz MCU clock, the following:
21 0xFFFFFFFF / (48^9 / 32 / 1000) [ms]
/Zephyr-latest/boards/st/stm32u083c_dk/doc/
Dindex.rst43 They operate at a frequency of up to 56 MHz.
57 - 52 µA/MHz Run mode (LDO mode)
62 - 32-bit Arm |reg| Cortex |reg|-M0+ CPU, frequency up to 56 MHz
70 - 1.13 DMIPS/MHz (Drystone 2.1)
71 - 134 CoreMark |reg| (2.4 CoreMark/MHz at 56 MHz)
87 - 4 to 48 MHz crystal oscillator
89 - Internal 16 MHz factory-trimmed RC (±1%)
91 - Internal multispeed 100 kHz to 48 MHz oscillator,
93 - Internal 48 MHz with clock recovery
132 - 8*48 or 4*52 segments, with step-up converter
[all …]
/Zephyr-latest/drivers/disk/
DKconfig.sdmmc66 bool "Runtime SDMMC 48MHz clock check"
70 Enable SDMMC clock 48MHz configuration runtime check.
/Zephyr-latest/soc/microchip/mec/mec172x/
Dpower.c27 * Lower power dissipation, 48MHz PLL is off
30 * between 16 to 25 MHz. Minimum 3ms until PLL reaches lock
31 * frequency of 48MHz.
42 * possibly polling the DUT then MEC1501 will not shut off its 48MHz
117 * Higher power dissipation, 48MHz PLL remains on.
/Zephyr-latest/boards/ene/kb1200_evb/doc/
Dindex.rst29 The KB1200 MCU is configured to use the 96Mhz internal oscillator with the
30 on-chip DPLL to generate a resulting EC clock rate of 96MHz/48MHz/24MHz/12MHz.
/Zephyr-latest/boards/st/nucleo_u083rc/doc/
Dindex.rst36 They operate at a frequency of up to 56 MHz.
50 - 52 µA/MHz Run mode
57 - 32-bit Arm |reg| Cortex |reg|-M0+ CPU, frequency up to 56 MHz
65 - 1.13 DMIPS/MHz (Drystone 2.1)
66 - 134 CoreMark |reg| (2.4 CoreMark/MHz at 56 MHz)
82 - 4 to 48 MHz crystal oscillator
84 - Internal 16 MHz factory-trimmed RC (±1%)
86 - Internal multispeed 100 kHz to 48 MHz oscillator,
88 - Internal 48 MHz with clock recovery
170 48MHz, driven by 4MHz medium speed internal oscillator.
/Zephyr-latest/boards/renesas/ek_ra4m1/doc/
Dindex.rst10 running up to 48 MHz with the following features:
16 - 48 MHz Arm® Cortex®-M4 core with Floating Point Unit (FPU)
33 - Main MCU oscillator crystals, providing precision 12.000 MHz and 32,768 Hz external reference
103 * Target Interface Speed: 4 MHz
119 …ontrollers-microprocessors/ra-cortex-m-mcus/ra4m1-32-bit-microcontrollers-48mhz-arm-cortex-m4-and-…
/Zephyr-latest/boards/st/nucleo_wl55jc/doc/
Dnucleo_wl55jc.rst12 (Arm® Cortex®-M4/M0+ at 48 MHz) in UFBGA73 package featuring:
15 - RF transceiver (150 MHz to 960 MHz frequency range) supporting LoRa®,
22 - 32 MHz HSE on-board oscillator
53 - Frequency range: 150 MHz to 960 MHz
70 execution from Flash memory, frequency up to 48 MHz, MPU
72 - 1.25 DMIPS/MHz (Dhrystone 2.1)
76 - Frequency up to 48 MHz, MPU
77 - 0.95 DMIPS/MHz (Dhrystone 2.1)
104 - 32 MHz crystal oscillator
107 - High-speed internal 16 MHz factory trimmed RC (± 1 %)
[all …]
/Zephyr-latest/boards/others/serpente/doc/
Dindex.rst14 - ATSAMD21E18A ARM Cortex-M0+ processor at 48 MHz
35 The SAMD21 MCU is configured to use the 8MHz internal oscillator
36 with the on-chip PLL generating the 48 MHz system clock.

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