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/Zephyr-latest/tests/bsim/bluetooth/ll/edtt/gatt_test_app/src/gatt/
Dservice_a_1.c4 * SPDX-License-Identifier: Apache-2.0
9 * This code is auto-generated from the Excel Workbook
44 '3', '3', '4', '4', '4', '4', '4', '5', '5', '5', '5', '5', '6',
45 '6', '6', '6', '6', '7', '7', '7', '7', '7', '8', '8', '8', '8',
48 '4', '4', '4', '4', '4', '5', '5', '5', '5', '5', '6', '6', '6',
49 '6', '6', '7', '7', '7', '7', '7', '8', '8', '8', '8', '8', '9',
51 '1', '2', '2', '2', '2', '2', '3', '3', '3', '3', '3', '4', '4',
52 '4', '4', '4', '5', '5', '5', '5', '5', '6', '6', '6', '6', '6',
55 '2', '2', '2', '2', '3', '3', '3', '3', '3', '4', '4', '4', '4',
56 '4', '5', '5', '5', '5', '5', '6', '6', '6', '6', '6', '7', '7',
[all …]
/Zephyr-latest/dts/arm/nuvoton/npcx/
Dnpcx-miwus-wui-map.dtsi4 * SPDX-License-Identifier: Apache-2.0
9 npcx-miwus-wui-map {
10 compatible = "nuvoton,npcx-miwu-wui-map";
14 wui_io80: wui0-1-0 {
17 wui_io81: wui0-1-1 {
20 wui_io82: wui0-1-2 {
23 wui_io83: wui0-1-3 {
26 wui_io87: wui0-1-7 {
31 wui_io90: wui0-2-0 {
34 wui_io91: wui0-2-1 {
[all …]
/Zephyr-latest/samples/shields/x_nucleo_53l0a1/src/
Ddisplay_7seg.h7 * SPDX-License-Identifier: Apache-2.0
15 * ---
17 * -2-
18 * 0| |6
19 * ---
20 * 4
25 #define CHAR_0 (BIT(0) | BIT(1) | BIT(3) | BIT(4) | BIT(5) | BIT(6))
26 #define CHAR_1 (BIT(5) | BIT(6))
27 #define CHAR_2 (BIT(0) | BIT(2) | BIT(3) | BIT(4) | BIT(5))
28 #define CHAR_3 (BIT(2) | BIT(3) | BIT(4) | BIT(5) | BIT(6))
[all …]
/Zephyr-latest/include/zephyr/dt-bindings/pinctrl/renesas/
Dpinctrl-r8a77961.h3 * Copyright (c) 2023-2024 EPAM Systems
5 * SPDX-License-Identifier: Apache-2.0
10 #include "pinctrl-rcar-common.h"
13 #define PIN_NONE -1
18 #define PIN_D4 RCAR_GP_PIN(0, 4)
20 #define PIN_D6 RCAR_GP_PIN(0, 6)
34 #define PIN_A4 RCAR_GP_PIN(1, 4)
36 #define PIN_A6 RCAR_GP_PIN(1, 6)
63 #define PIN_IRQ4 RCAR_GP_PIN(2, 4)
65 #define PIN_PWM0 RCAR_GP_PIN(2, 6)
[all …]
Dpinctrl-r8a77951.h4 * SPDX-License-Identifier: Apache-2.0
9 #include "pinctrl-rcar-common.h"
12 #define PIN_NONE -1
17 #define PIN_D4 RCAR_GP_PIN(0, 4)
19 #define PIN_D6 RCAR_GP_PIN(0, 6)
33 #define PIN_A4 RCAR_GP_PIN(1, 4)
35 #define PIN_A6 RCAR_GP_PIN(1, 6)
62 #define PIN_IRQ4 RCAR_GP_PIN(2, 4)
64 #define PIN_PWM0 RCAR_GP_PIN(2, 6)
77 #define PIN_SD0_DATA2 RCAR_GP_PIN(3, 4)
[all …]
/Zephyr-latest/samples/subsys/nvs/
Dsample.yaml10 - nrf52dk/nrf52832
15 - "Id: 1, Address: 192.168.1.1"
16 - "Id: 2, Key: ff fe fd fc fb fa f9 f8"
17 - "Id: 3, Reboot_counter: (.*)"
18 - "Id: 4, Data: DATA"
19 - "Id: 5, Longarray: 0 1 2 3 4 5 6 7 8 9 a b c d e f 10 11 12 13 14 15 16 17 18 19 1a 1b \
21 39 3a 3b 3c 3d 3e 3f 40 41 42 43 44 45 46 47 48 49 4a 4b 4c 4d 4e 4f 50 51 52 53 54 55 \
22 56 57 58 59 5a 5b 5c 5d 5e 5f 60 61 62 63 64 65 66 67 68 69 6a 6b 6c 6d 6e 6f 70 71 72 \
/Zephyr-latest/drivers/ieee802154/
Dieee802154_rf2xx_regs.h1 /* ieee802154_rf2xx_regs.h - ATMEL RF2XX transceiver registers */
6 * SPDX-License-Identifier: Apache-2.0
12 /*- Definitions ------------------------------------------------------------*/
23 #define RX2XX_FRAME_TRAC_INDEX 4
27 #define RF2XX_RSSI_BPSK_20 -100
28 #define RF2XX_RSSI_BPSK_40 -99
29 #define RF2XX_RSSI_OQPSK_SIN_RC_100 -98
30 #define RF2XX_RSSI_OQPSK_SIN_250 -97
31 #define RF2XX_RSSI_OQPSK_RC_250 -97
33 /*- Types ------------------------------------------------------------------*/
[all …]
/Zephyr-latest/dts/arm/infineon/cat3/xmc/
Dxmc4500_F100x1024-intc.dtsi3 * SPDX-License-Identifier: Apache-2.0
6 #include <zephyr/dt-bindings/interrupt-controller/infineon-xmc4xxx-intc.h>
9 port-line-mapping = <
13 XMC4XXX_INTC_SET_LINE_MAP(0, 0, 4, 0) /* ERU0_ETL0_INPUTB_P0_0 XMC_ERU_ETL_INPUT_B0 */
15 XMC4XXX_INTC_SET_LINE_MAP(2, 4, 6, 0) /* ERU0_ETL0_INPUTB_P2_4 XMC_ERU_ETL_INPUT_B2 */
19 XMC4XXX_INTC_SET_LINE_MAP(0, 9, 4, 1) /* ERU0_ETL1_INPUTB_P0_9 XMC_ERU_ETL_INPUT_B0 */
20 XMC4XXX_INTC_SET_LINE_MAP(2, 2, 6, 1) /* ERU0_ETL1_INPUTB_P2_2 XMC_ERU_ETL_INPUT_B2 */
21 XMC4XXX_INTC_SET_LINE_MAP(2, 6, 7, 1) /* ERU0_ETL1_INPUTB_P2_6 XMC_ERU_ETL_INPUT_B3 */
24 XMC4XXX_INTC_SET_LINE_MAP(0, 12, 6, 2) /* ERU0_ETL2_INPUTB_P0_12 XMC_ERU_ETL_INPUT_B2 */
25 XMC4XXX_INTC_SET_LINE_MAP(0, 4, 7, 2) /* ERU0_ETL2_INPUTB_P0_4 XMC_ERU_ETL_INPUT_B3 */
[all …]
Dxmc4700_F144x2048-intc.dtsi3 * SPDX-License-Identifier: Apache-2.0
6 #include <zephyr/dt-bindings/interrupt-controller/infineon-xmc4xxx-intc.h>
9 port-line-mapping = <
13 XMC4XXX_INTC_SET_LINE_MAP(0, 0, 4, 0) /* ERU0_ETL0_INPUTB_P0_0 XMC_ERU_ETL_INPUT_B0 */
15 XMC4XXX_INTC_SET_LINE_MAP(2, 4, 6, 0) /* ERU0_ETL0_INPUTB_P2_4 XMC_ERU_ETL_INPUT_B2 */
19 XMC4XXX_INTC_SET_LINE_MAP(0, 9, 4, 1) /* ERU0_ETL1_INPUTB_P0_9 XMC_ERU_ETL_INPUT_B0 */
20 XMC4XXX_INTC_SET_LINE_MAP(2, 2, 6, 1) /* ERU0_ETL1_INPUTB_P2_2 XMC_ERU_ETL_INPUT_B2 */
21 XMC4XXX_INTC_SET_LINE_MAP(2, 6, 7, 1) /* ERU0_ETL1_INPUTB_P2_6 XMC_ERU_ETL_INPUT_B3 */
25 XMC4XXX_INTC_SET_LINE_MAP(0, 12, 6, 2) /* ERU0_ETL2_INPUTB_P0_12 XMC_ERU_ETL_INPUT_B2 */
26 XMC4XXX_INTC_SET_LINE_MAP(0, 4, 7, 2) /* ERU0_ETL2_INPUTB_P0_4 XMC_ERU_ETL_INPUT_B3 */
[all …]
/Zephyr-latest/dts/arm/nuvoton/npcx/npcx4/
Dnpcx4-miwus-wui-map.dtsi4 * SPDX-License-Identifier: Apache-2.0
7 /* Common Wake-Up Unit Input (WUI) mapping configurations in npcx family */
8 #include <nuvoton/npcx/npcx-miwus-wui-map.dtsi>
10 /* Specific Wake-Up Unit Input (WUI) mapping configurations in npcx4 series */
13 npcx-miwus-wui-map {
14 compatible = "nuvoton,npcx-miwu-wui-map";
18 wui_ioe7: wui0-8-7 {
24 wui_io13: wui1-2-3 {
29 wui_io66: wui1-7-6 {
30 miwus = <&miwu1 6 6>; /* GPIO66 */
[all …]
/Zephyr-latest/drivers/sensor/st/lsm9ds0_mfd/
Dlsm9ds0_mfd.h1 /* sensor_lsm9ds0_mfd.h - header file for LSM9DS0 accelerometer, magnetometer
8 * SPDX-License-Identifier: Apache-2.0
24 #define LSM9DS0_MFD_MASK_STATUS_REG_M_ZMOR BIT(6)
25 #define LSM9DS0_MFD_SHIFT_STATUS_REG_M_ZMOR 6
28 #define LSM9DS0_MFD_MASK_STATUS_REG_M_XMOR BIT(4)
29 #define LSM9DS0_MFD_SHIFT_STATUS_REG_M_XMOR 4
52 #define LSM9DS0_MFD_MASK_INT_CTRL_REG_M_YMIEN BIT(6)
53 #define LSM9DS0_MFD_SHIFT_INT_CTRL_REG_M_YMIEN 6
56 #define LSM9DS0_MFD_MASK_INT_CTRL_REG_M_PP_OD BIT(4)
57 #define LSM9DS0_MFD_SHIFT_INT_CTRL_REG_M_PP_OD 4
[all …]
/Zephyr-latest/drivers/sensor/st/lsm9ds0_gyro/
Dlsm9ds0_gyro.h1 /* sensor_lsm9ds0_gyro.h - header file for LSM9DS0 gyroscope sensor driver */
6 * SPDX-License-Identifier: Apache-2.0
23 #define LSM9DS0_GYRO_MASK_CTRL_REG1_G_DR (BIT(7) | BIT(6))
24 #define LSM9DS0_GYRO_SHIFT_CTRL_REG1_G_DR 6
25 #define LSM9DS0_GYRO_MASK_CTRL_REG1_G_BW (BIT(5) | BIT(4))
26 #define LSM9DS0_GYRO_SHIFT_CTRL_REG1_G_BW 4
37 #define LSM9DS0_GYRO_MASK_CTRL_REG2_G_HPM (BIT(5) | BIT(4))
38 #define LSM9DS0_GYRO_SHIFT_CTRL_REG2_G_HPM 4
45 #define LSM9DS0_GYRO_MASK_CTRL_REG3_G_I1_BOOT BIT(6)
46 #define LSM9DS0_GYRO_SHIFT_CTRL_REG3_G_I1_BOOT 6
[all …]
/Zephyr-latest/tests/net/traffic_class/
Dtestcase.yaml3 - native_sim
4 - native_sim/native/64
6 - native_sim/native/64
8 - net
9 - traffic_class
13 - CONFIG_NET_TC_TX_COUNT=1
14 - CONFIG_NET_TC_RX_COUNT=1
17 - CONFIG_NET_TC_TX_COUNT=2
18 - CONFIG_NET_TC_RX_COUNT=2
21 - CONFIG_NET_TC_TX_COUNT=3
[all …]
/Zephyr-latest/include/zephyr/dt-bindings/clock/
Dnpcm_clock.h4 * SPDX-License-Identifier: Apache-2.0
16 #define NPCM_CLOCK_UART2 (NPCM_CLOCK_GROUP_OFFSET(0) + 6)
20 #define NPCM_CLOCK_UART (NPCM_CLOCK_GROUP_OFFSET(1) + 4)
22 #define NPCM_CLOCK_MFT2 (NPCM_CLOCK_GROUP_OFFSET(1) + 6)
28 #define NPCM_CLOCK_PWM_E (NPCM_CLOCK_GROUP_OFFSET(2) + 4)
30 #define NPCM_CLOCK_PWM_G (NPCM_CLOCK_GROUP_OFFSET(2) + 6)
36 #define NPCM_CLOCK_SMB5 (NPCM_CLOCK_GROUP_OFFSET(3) + 4)
39 #define NPCM_CLOCK_ITIM1 (NPCM_CLOCK_GROUP_OFFSET(4) + 0)
40 #define NPCM_CLOCK_ITIM2 (NPCM_CLOCK_GROUP_OFFSET(4) + 1)
41 #define NPCM_CLOCK_ITIM3 (NPCM_CLOCK_GROUP_OFFSET(4) + 2)
[all …]
/Zephyr-latest/drivers/sensor/st/lsm6dsl/
Dlsm6dsl.h1 /* sensor_lsm6dsl.h - header file for LSM6DSL accelerometer, gyroscope and
8 * SPDX-License-Identifier: Apache-2.0
44 #define LSM6DSL_MASK_FIFO_CTRL1_FTH (BIT(7) | BIT(6) | \
45 BIT(5) | BIT(4) | \
53 #define LSM6DSL_MASK_FIFO_CTRL2_TIMER_PEDO_FIFO_DRDY BIT(6)
54 #define LSM6DSL_SHIFT_FIFO_CTRL2_TIMER_PEDO_FIFO_DRDY 6
62 #define LSM6DSL_MASK_FIFO_CTRL3_DEC_FIFO_GYRO (BIT(5) | BIT(4) | \
72 #define LSM6DSL_MASK_FIFO_CTRL4_ONLY_HIGH_DATA BIT(6)
73 #define LSM6DSL_SHIFT_FIFO_CTRL4_ONLY_HIGH_DATA 6
74 #define LSM6DSL_MASK_FIFO_CTRL4_DEC_DS4_FIFO (BIT(5) | BIT(4) | \
[all …]
/Zephyr-latest/drivers/audio/
Dtas6422dac.h4 * SPDX-License-Identifier: Apache-2.0
20 #define MODE_CTRL_PBTL_CH12 BIT(4)
21 #define MODE_CTRL_PBTL_CH12_MASK BIT(4)
37 #define MISC_CTRL_1_OC_CONTROL BIT(4)
38 #define MISC_CTRL_1_OC_CONTROL_MASK BIT(4)
54 #define MISC_CTRL_2_PWM_FREQUENCY_MASK (BIT_MASK(3) << 4)
55 #define MISC_CTRL_2_PWM_FREQUENCY(val) (((val) << 4) & MISC_CTRL_2_PWM_FREQUENCY_MASK)
59 #define MISC_CTRL_2_PWM_FREQUENCY_44_FS 6
69 /* Serial Audio-Port Control Register */
71 #define SAP_CTRL_INPUT_SAMPLING_RATE_MASK (BIT_MASK(2) << 6)
[all …]
/Zephyr-latest/dts/bindings/clock/
Dnuvoton,npcx-pcc.yaml2 # SPDX-License-Identifier: Apache-2.0
8 High-Frequency Clock Generator (HFCG), is the source clock of Cortex-M4 core
14 clock-frequency = <DT_FREQ_M(100)>; /* OFMCLK runs at 100MHz */
15 core-prescaler = <5>; /* CORE_CLK runs at 20MHz */
16 apb1-prescaler = <5>; /* APB1_CLK runs at 20MHz */
17 apb2-prescaler = <5>; /* APB2_CLK runs at 20MHz */
18 apb3-prescaler = <5>; /* APB3_CLK runs at 20MHz */
21 compatible: "nuvoton,npcx-pcc"
23 include: [clock-controller.yaml, base.yaml]
29 clock-frequency:
[all …]
/Zephyr-latest/drivers/sensor/st/lsm6ds0/
Dlsm6ds0.h1 /* sensor_lsm6ds0.h - header file for LSM6DS0 accelerometer, gyroscope and
8 * SPDX-License-Identifier: Apache-2.0
21 #define LSM6DS0_MASK_ACT_THS_ACT_THS (BIT(6) | BIT(5) | BIT(4) | \
31 #define LSM6DSO_MASK_INT_GEN_CFG_XL_6D BIT(6)
32 #define LSM6DS0_SHIFT_INT_GEN_CFG_XL_6D 6
35 #define LSM6DS0_MASK_INT_GEN_CFG_XL_ZLIE_XL BIT(4)
36 #define LSM6DS0_SHIFT_INT_GEN_CFG_XL_ZLIE_XL 4
55 #define LSM6DS0_MASK_INT_CTRL_INT_IG_XL BIT(6)
56 #define LSM6DS0_SHIFT_INT_CTRL_INT_IG_XL 6
59 #define LSM6DS0_MASK_INT_CTRL_INT_OVR BIT(4)
[all …]
/Zephyr-latest/boards/renesas/ek_ra8d1/
Dek_ra8d1-pinctrl.dtsi3 * SPDX-License-Identifier: Apache-2.0
11 drive-strength = "medium";
22 psels = <RA_PSEL(RA_PSEL_SPI, 4, 10)>,
23 <RA_PSEL(RA_PSEL_SPI, 4, 11)>,
24 <RA_PSEL(RA_PSEL_SPI, 4, 12)>,
25 <RA_PSEL(RA_PSEL_SPI, 4, 13)>;
36 psels = <RA_PSEL(RA_PSEL_GPT1, 10, 6)>;
43 psels = <RA_PSEL(RA_PSEL_CANFD, 4, 2)>,
44 <RA_PSEL(RA_PSEL_CANFD, 4, 1)>;
45 drive-strength = "high";
[all …]
/Zephyr-latest/samples/subsys/fs/zms/
DREADME.rst1 .. zephyr:code-sample:: zms
3 :relevant-api: zms_high_level_api
40 .. zephyr-app-commands::
41 :zephyr-app: samples/subsys/fs/zms
51 .. code-block:: console
53 *** Booting Zephyr OS build v3.7.0-2383-g624f75400242 ***
72 …4 5 6 7 8 9 a b c d e f 10 11 12 13 14 15 16 17 18 19 1a 1b 1c 1d 1e 1f 20 21 22 23 24 25 26 27 28…
73 …4 55 56 57 58 59 5a 5b 5c 5d 5e 5f 60 61 62 63 64 65 66 67 68 69 6a 6b 6c 6d 6e 6f 70 71 72 73 74 …
91 …4 5 6 7 8 9 a b c d e f 10 11 12 13 14 15 16 17 18 19 1a 1b 1c 1d 1e 1f 20 21 22 23 24 25 26 27 28…
92 …4 55 56 57 58 59 5a 5b 5c 5d 5e 5f 60 61 62 63 64 65 66 67 68 69 6a 6b 6c 6d 6e 6f 70 71 72 73 74 …
/Zephyr-latest/dts/bindings/sensor/
Dti,ina3221.yaml2 # SPDX-License-Identifier: Apache-2.0
4 description: Texas Instruments INA3221 Triple-Channel Current/Power Monitor
8 include: [sensor-device.yaml, i2c-device.yaml]
11 conv-time-shunt:
13 default: 4
15 Shunt-voltage conversion time.
16 The default of 1.1 ms is the power-on reset value of the device.
21 4 = 1.1 ms (default)
23 6 = 4.156 ms
26 - 0
[all …]
/Zephyr-latest/drivers/pinctrl/renesas/rcar/
Dpfc_r8a77951.c2 * Copyright (c) 2021-2023 IoT.bzh
4 * SPDX-License-Identifier: Apache-2.0
9 #include <zephyr/dt-bindings/pinctrl/renesas/pinctrl-r8a77951.h>
20 { PIN_QSPI1_SPCLK, 4, 2 }, /* QSPI1_SPCLK */
31 { PIN_RPC_RESET_N, 4, 2 }, /* RPC_RESET# */
42 { PIN_AVB_TXC, 4, 3 }, /* AVB_TXC */
53 { RCAR_GP_PIN(2, 10), 4, 3 }, /* AVB_MAGIC */
64 { RCAR_GP_PIN(2, 3), 4, 3 }, /* IRQ3 */
65 { RCAR_GP_PIN(2, 4), 0, 3 }, /* IRQ4 */
70 { RCAR_GP_PIN(2, 6), 24, 3 }, /* PWM0 */
[all …]
Dpfc_r8a77961.c2 * Copyright (c) 2021-2023 IoT.bzh
4 * SPDX-License-Identifier: Apache-2.0
9 #include <zephyr/dt-bindings/pinctrl/renesas/pinctrl-r8a77961.h>
20 { PIN_QSPI1_SPCLK, 4, 2 }, /* QSPI1_SPCLK */
31 { PIN_RPC_RESET_N, 4, 2 }, /* RPC_RESET# */
42 { PIN_AVB_TXC, 4, 3 }, /* AVB_TXC */
53 { RCAR_GP_PIN(2, 10), 4, 3 }, /* AVB_MAGIC */
64 { RCAR_GP_PIN(2, 3), 4, 3 }, /* IRQ3 */
65 { RCAR_GP_PIN(2, 4), 0, 3 }, /* IRQ4 */
70 { RCAR_GP_PIN(2, 6), 24, 3 }, /* PWM0 */
[all …]
/Zephyr-latest/include/zephyr/dt-bindings/pinctrl/
Dambiq-apollo4-pinctrl.h4 * SPDX-License-Identifier: Apache-2.0
13 #define APOLLO4_PIN_NUM_POS 4
23 #define UART0TX_P0 APOLLO4_PINMUX(0, 4)
25 #define CT0_P0 APOLLO4_PINMUX(0, 6)
34 #define UART2TX_P1 APOLLO4_PINMUX(1, 4)
36 #define CT1_P1 APOLLO4_PINMUX(1, 6)
46 #define UART0RX_P2 APOLLO4_PINMUX(2, 4)
48 #define CT2_P2 APOLLO4_PINMUX(2, 6)
58 #define UART2RX_P3 APOLLO4_PINMUX(3, 4)
60 #define CT3_P3 APOLLO4_PINMUX(3, 6)
[all …]
Dambiq-apollo3-pinctrl.h4 * SPDX-License-Identifier: Apache-2.0
13 #define APOLLO3_PIN_NUM_POS 4
42 #define TRIG1_P3 APOLLO3_PINMUX(3, 6)
44 #define UA0CTS_P4 APOLLO3_PINMUX(4, 0)
45 #define SLINT_P4 APOLLO3_PINMUX(4, 1)
46 #define NCE4_P4 APOLLO3_PINMUX(4, 2)
47 #define GPIO_P4 APOLLO3_PINMUX(4, 3)
48 #define UART1RX_P4 APOLLO3_PINMUX(4, 5)
49 #define CTIM17_P4 APOLLO3_PINMUX(4, 6)
50 #define MSPI0_2_P4 APOLLO3_PINMUX(4, 7)
[all …]

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