Lines Matching +full:4 +full:- +full:6
4 * SPDX-License-Identifier: Apache-2.0
20 #define MODE_CTRL_PBTL_CH12 BIT(4)
21 #define MODE_CTRL_PBTL_CH12_MASK BIT(4)
37 #define MISC_CTRL_1_OC_CONTROL BIT(4)
38 #define MISC_CTRL_1_OC_CONTROL_MASK BIT(4)
54 #define MISC_CTRL_2_PWM_FREQUENCY_MASK (BIT_MASK(3) << 4)
55 #define MISC_CTRL_2_PWM_FREQUENCY(val) (((val) << 4) & MISC_CTRL_2_PWM_FREQUENCY_MASK)
59 #define MISC_CTRL_2_PWM_FREQUENCY_44_FS 6
69 /* Serial Audio-Port Control Register */
71 #define SAP_CTRL_INPUT_SAMPLING_RATE_MASK (BIT_MASK(2) << 6)
72 #define SAP_CTRL_INPUT_SAMPLING_RATE(val) (((val) << 6) & SAP_CTRL_INPUT_SAMPLING_RATE_MASK)
78 #define SAP_CTRL_TDM_SLOT_SIZE BIT(4)
79 #define SAP_CTRL_TDM_SLOT_SIZE_MASK BIT(4)
88 #define SAP_CTRL_INPUT_FORMAT_I2S 4
90 #define SAP_CTRL_INPUT_FORMAT_DSP 6
94 #define CH_STATE_CTRL_CH1_STATE_CTRL_MASK (BIT_MASK(2) << 6)
95 #define CH_STATE_CTRL_CH1_STATE_CTRL(val) (((val) << 6) & CH_STATE_CTRL_CH1_STATE_CTRL_MASK)
96 #define CH_STATE_CTRL_CH2_STATE_CTRL_MASK (BIT_MASK(2) << 4)
97 #define CH_STATE_CTRL_CH2_STATE_CTRL(val) (((val) << 4) & CH_STATE_CTRL_CH2_STATE_CTRL_MASK)
113 #define DC_LDG_CTRL_1_DOUBLE_RAMP BIT(6)
114 #define DC_LDG_CTRL_1_DOUBLE_RAMP_MASK BIT(6)
124 #define DC_LDG_CTRL_2_CH1_SL_MASK (BIT_MASK(4) << 4)
125 #define DC_LDG_CTRL_2_CH1_SL(val) (((val) << 4) & DC_LDG_CTRL_2_CH1_SL_MASK)
126 #define DC_LDG_CTRL_2_CH2_SL_MASK BIT_MASK(4)
133 #define DC_LDG_REPORT_1_CH1_S2P BIT(6)
134 #define DC_LDG_REPORT_1_CH1_S2P_MASK BIT(6)
137 #define DC_LDG_REPORT_1_CH1_SL BIT(4)
138 #define DC_LDG_REPORT_1_CH1_SL_MASK BIT(4)
159 #define CH_FAULTS_CH2_OC BIT(6)
160 #define CH_FAULTS_CH2_OC_MASK BIT(6)
168 #define GLOBAL_FAULTS_1_INVALID_CLOCK BIT(4)
169 #define GLOBAL_FAULTS_1_INVALID_CLOCK_MASK BIT(4)
181 #define GLOBAL_FAULTS_2_OTSD BIT(4)
182 #define GLOBAL_FAULTS_2_OTSD_MASK BIT(4)
192 #define WARNINGS_OTW BIT(4)
193 #define WARNINGS_OTW_MASK BIT(4)
203 #define PIN_CTRL_MASK_OTSD BIT(6)
204 #define PIN_CTRL_MASK_OTSD_MASK BIT(6)
207 #define PIN_CTRL_MASK_OV BIT(4)
208 #define PIN_CTRL_MASK_OV_MASK BIT(4)
222 #define MISC_CTRL_3_PBTL_CH_SEL BIT(6)
223 #define MISC_CTRL_3_PBTL_CH_SEL_MASK BIT(6)
236 /* Miscellaneous Control 4 Register */
244 #define MISC_CTRL_4_HPF_CORNER_59_HZ 4
246 #define MISC_CTRL_4_HPF_CORNER_235_HZ 6
253 #define MISC_CTRL_5_SS_DIV2 BIT(6)
254 #define MISC_CTRL_5_SS_DIV2_MASK BIT(6)