Lines Matching +full:4 +full:- +full:6
1 /* sensor_lsm6ds0.h - header file for LSM6DS0 accelerometer, gyroscope and
8 * SPDX-License-Identifier: Apache-2.0
21 #define LSM6DS0_MASK_ACT_THS_ACT_THS (BIT(6) | BIT(5) | BIT(4) | \
31 #define LSM6DSO_MASK_INT_GEN_CFG_XL_6D BIT(6)
32 #define LSM6DS0_SHIFT_INT_GEN_CFG_XL_6D 6
35 #define LSM6DS0_MASK_INT_GEN_CFG_XL_ZLIE_XL BIT(4)
36 #define LSM6DS0_SHIFT_INT_GEN_CFG_XL_ZLIE_XL 4
55 #define LSM6DS0_MASK_INT_CTRL_INT_IG_XL BIT(6)
56 #define LSM6DS0_SHIFT_INT_CTRL_INT_IG_XL 6
59 #define LSM6DS0_MASK_INT_CTRL_INT_OVR BIT(4)
60 #define LSM6DS0_SHIFT_INT_CTRL_INT_OVR 4
74 #define LSM6DS0_MASK_CTRL_REG1_G_ODR_G (BIT(7) | BIT(6) | BIT(5))
76 #define LSM6DS0_MASK_CTRL_REG1_G_FS_G (BIT(4) | BIT(3))
90 #define LSM6DS0_MASK_CTRL_REG3_G_HP_EN BIT(6)
91 #define LSM6DS0_SHIFT_CTRL_REG3_G_HP_EN 6
99 #define LSM6DS0_MASK_ORIENT_CFG_G_SIGNY_G BIT(4)
100 #define LSM6DS0_SHIFT_ORIENT_CFG_G_SIGNY_G 4
107 #define LSM6DS0_MASK_INT_GEN_SRC_G_IA_G BIT(6)
108 #define LSM6DS0_SHIFT_INT_GEN_SRC_G_IA_G 6
111 #define LSM6DS0_MASK_INT_GEN_SRC_G_ZL_G BIT(4)
112 #define LSM6DS0_SHIFT_INT_GEN_SRC_G_ZL_G 4
126 #define LSM6DS0_MASK_STATUS_REG_G_IG_XL BIT(6)
127 #define LSM6DS0_SHIFT_STATUS_REG_G_IG_XL 6
130 #define LSM6DS0_MASK_STATUS_REG_G_INACT BIT(4)
131 #define LSM6DS0_SHIFT_STATUS_REG_G_INACT 4
151 #define LSM6DS0_MASK_CTRL_REG4_YEN_G BIT(4)
152 #define LSM6DS0_SHIFT_CTRL_REG4_YEN_G 4
161 #define LSM6DS0_MASK_CTRL_REG5_XL_DEC (BIT(7) | BIT(6))
162 #define LSM6DS0_SHIFT_CTRL_REG5_XL_DEC 6
165 #define LSM6DS0_MASK_CTRL_REG5_XL_YEN_XL BIT(4)
166 #define LSM6DS0_SHIFT_CTRL_REG5_XL_YEN_XL 4
171 #define LSM6DS0_MASK_CTRL_REG6_XL_ODR_XL (BIT(7) | BIT(6) | BIT(5))
173 #define LSM6DS0_MASK_CTRL_REG6_XL_FS_XL (BIT(4) | BIT(3))
183 #define LSM6DS0_MASK_CTRL_REG7_XL_DCF (BIT(6) | BIT(5))
193 #define LSM6DS0_MASK_CTRL_REG8_BDU BIT(6)
194 #define LSM6DS0_SHIFT_CTRL_REG8_BDU 6
197 #define LSM6DS0_MASK_CTRL_REG8_PP_OD BIT(4)
198 #define LSM6DS0_SHIFT_CTRL_REG8_PP_OD 4
209 #define LSM6DS0_MASK_CTRL_REG9_SLEEP_G BIT(6)
210 #define LSM6DS0_SHIFT_CTRL_REG9_SLEEP_G 6
211 #define LSM6DS0_MASK_CTRL_REG9_FIFO_TEMP_EN BIT(4)
212 #define LSM6DS0_SHIFT_CTRL_REG9_FIFO_TEMP_EN 4
229 #define LSM6DS0_MASK_INT_GEN_SRC_XL_IA_XL BIT(6)
230 #define LSM6DS0_SHIFT_INT_GEN_SRC_XL_IA_XL 6
233 #define LSM6DS0_MASK_INT_GEN_SRC_XL_ZL_XL BIT(4)
234 #define LSM6DS0_SHIFT_INT_GEN_SRC_XL_ZL_XL 4
245 #define LSM6DS0_MASK_STATUS_REG_XL_IG_XL BIT(6)
246 #define LSM6DS0_SHIFT_STATUS_REG_XL_IG_XL 6
249 #define LSM6DS0_MASK_STATUS_REG_XL_INACT BIT(4)
250 #define LSM6DS0_SHIFT_STATUS_REG_XL_INACT 4
268 #define LSM6DS0_MASK_FIFO_CTRL_FMODE (BIT(7) | BIT(6) | BIT(5))
270 #define LSM6DS0_MASK_FIFO_CTRL_FTH (BIT(4) | BIT(3) | BIT(2) | \
277 #define LSM6DS0_MASK_FIFO_SRC_OVRN BIT(6)
278 #define LSM6DS0_SHIFT_FIFO_SRC_OVRN 6
279 #define LSM6DS0_MASK_FIFO_SRC_FSS (BIT(5) | BIT(4) | BIT(3) | \
286 #define LSM6DS0_MASK_INT_GEN_CFG_G_LIR_G BIT(6)
287 #define LSM6DS0_SHIFT_INT_GEN_CFG_G_LIR_G 6
290 #define LSM6DS0_MASK_INT_GEN_CFG_G_ZLIE_G BIT(4)
291 #define LSM6DS0_SHIFT_INT_GEN_CFG_G_ZLIE_G 4
357 #elif CONFIG_LSM6DS0_ACCEL_FULLSCALE == 4
404 #define LSM6DS0_DEFAULT_ACCEL_SAMPLING_RATE 4
408 #define LSM6DS0_DEFAULT_ACCEL_SAMPLING_RATE 6
455 #define LSM6DS0_DEFAULT_GYRO_SAMPLING_RATE 4
459 #define LSM6DS0_DEFAULT_GYRO_SAMPLING_RATE 6