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/Zephyr-latest/include/zephyr/dt-bindings/pinctrl/
Drpi-pico-rp2350b-pinctrl.h4 * SPDX-License-Identifier: Apache-2.0
10 #include "rpi-pico-rp2350-pinctrl-common.h"
12 /* RP2350B is in a QFN-80 package, and extends the set of available pins
24 #define SPI0_TX_P39 RP2XXX_PINMUX(39, RP2_PINCTRL_GPIO_FUNC_SPI)
25 #define SPI1_RX_P40 RP2XXX_PINMUX(40, RP2_PINCTRL_GPIO_FUNC_SPI)
43 #define UART1_RX_P39 RP2XXX_PINMUX(39, RP2_PINCTRL_GPIO_FUNC_UART)
44 #define UART0_TX_P40 RP2XXX_PINMUX(40, RP2_PINCTRL_GPIO_FUNC_UART)
62 #define I2C1_SCL_P39 RP2XXX_PINMUX(39, RP2_PINCTRL_GPIO_FUNC_I2C)
63 #define I2C0_SDA_P40 RP2XXX_PINMUX(40, RP2_PINCTRL_GPIO_FUNC_I2C)
81 #define PWM_11B_P39 RP2XXX_PINMUX(39, RP2_PINCTRL_GPIO_FUNC_PWM)
[all …]
Desp32s2-pinctrl.h4 * SPDX-License-Identifier: Apache-2.0
119 ESP32_PINMUX(39, ESP_I2CEXT0_SCL_IN, ESP_I2CEXT0_SCL_OUT)
122 ESP32_PINMUX(40, ESP_I2CEXT0_SCL_IN, ESP_I2CEXT0_SCL_OUT)
246 ESP32_PINMUX(39, ESP_I2CEXT0_SDA_IN, ESP_I2CEXT0_SDA_OUT)
249 ESP32_PINMUX(40, ESP_I2CEXT0_SDA_IN, ESP_I2CEXT0_SDA_OUT)
373 ESP32_PINMUX(39, ESP_I2CEXT1_SCL_IN, ESP_I2CEXT1_SCL_OUT)
376 ESP32_PINMUX(40, ESP_I2CEXT1_SCL_IN, ESP_I2CEXT1_SCL_OUT)
500 ESP32_PINMUX(39, ESP_I2CEXT1_SDA_IN, ESP_I2CEXT1_SDA_OUT)
503 ESP32_PINMUX(40, ESP_I2CEXT1_SDA_IN, ESP_I2CEXT1_SDA_OUT)
627 ESP32_PINMUX(39, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0)
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Desp32s3-pinctrl.h4 * SPDX-License-Identifier: Apache-2.0
83 #define I2C0_SCL_GPIO39 ESP32_PINMUX(39, ESP_I2CEXT0_SCL_IN, ESP_I2CEXT0_SCL_OUT)
85 #define I2C0_SCL_GPIO40 ESP32_PINMUX(40, ESP_I2CEXT0_SCL_IN, ESP_I2CEXT0_SCL_OUT)
174 #define I2C0_SDA_GPIO39 ESP32_PINMUX(39, ESP_I2CEXT0_SDA_IN, ESP_I2CEXT0_SDA_OUT)
176 #define I2C0_SDA_GPIO40 ESP32_PINMUX(40, ESP_I2CEXT0_SDA_IN, ESP_I2CEXT0_SDA_OUT)
265 #define I2C1_SCL_GPIO39 ESP32_PINMUX(39, ESP_I2CEXT1_SCL_IN, ESP_I2CEXT1_SCL_OUT)
267 #define I2C1_SCL_GPIO40 ESP32_PINMUX(40, ESP_I2CEXT1_SCL_IN, ESP_I2CEXT1_SCL_OUT)
356 #define I2C1_SDA_GPIO39 ESP32_PINMUX(39, ESP_I2CEXT1_SDA_IN, ESP_I2CEXT1_SDA_OUT)
358 #define I2C1_SDA_GPIO40 ESP32_PINMUX(40, ESP_I2CEXT1_SDA_IN, ESP_I2CEXT1_SDA_OUT)
447 #define I2S0_I_BCK_GPIO39 ESP32_PINMUX(39, ESP_I2S0I_BCK_IN, ESP_I2S0I_BCK_OUT)
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Dsmartbond-pinctrl.h4 * SPDX-License-Identifier: Apache-2.0
50 #define SMARTBOND_FUNC_PORT2_DCF 39
51 #define SMARTBOND_FUNC_PORT3_DCF 40
Dsi32-pinctrl.h4 * SPDX-License-Identifier: Apache-2.0
63 #define SI32_SIGNAL_TIMER1_EX 39
65 #define SI32_SIGNAL_UART0_TX 40
Desp32c3-gpio-sigmap.h4 * SPDX-License-Identifier: Apache-2.0
70 #define ESP_BB_DIAG19 39
71 #define ESP_USB_EXTPHY_VP 40
72 #define ESP_USB_EXTPHY_OEN 40
/Zephyr-latest/dts/bindings/gpio/
Dti,boosterpack-header.yaml2 # SPDX-License-Identifier: Apache-2.0
9 BoosterPack plug-in modules are available in 20 and 40 pin variants. The
10 20 pin variant has two 10 x 1 pin headers and the 40 pin variant has two
13 The pins of the 20 pin variant and the outer row of the 40 pin variant are
14 numbered 1 through 20. The inner rows of the 40 pin variant are numbered 21
15 through 40. The BoosterPack pinout is depicted below:
17 1 3.3V 21 5V 40 GPIO 20 GND
18 2 Analog 22 GND 39 GPIO 19 GPIO / SPI CS
32 compatible: "ti,boosterpack-header"
34 include: [gpio-nexus.yaml, base.yaml]
Dnxp,cam-44pins-connector.yaml2 # SPDX-License-Identifier: Apache-2.0
5 GPIO pins exposed on NXP 44-pin board-to-board camera connector.
28 40 DGND DGND 39
31 compatible: "nxp,cam-44pins-connector"
33 include: [gpio-nexus.yaml, base.yaml]
Dadi,sdp-120.yaml4 # SPDX-License-Identifier: Apache-2.0
9 120-pin SDP interface:
49 39 SPI_SEL1/SPI_SS_N SPI_CLK 82
50 40 GND GND 81
72 compatible: "adi,sdp-120"
74 include: [gpio-nexus.yaml, base.yaml]
Dst,dsi-lcd-qsh-030.yaml2 # SPDX-License-Identifier: Apache-2.0
5 GPIO pins exposed on QSH-030-01-F-D-A connector used as DSI LCD connector.
9 (1) GND - (2)
11 (5) DSI_CK_N - (6)
12 (7) GND - (8)
13 (9) DSI_D0_P - (10)
14 (11) DSI_D0_N - (12)
15 (13) GND - (14)
16 (15) DSI_D1_P - (16)
17 (17) DSI_D1_N - (18)
[all …]
/Zephyr-latest/soc/xlnx/zynq7000/common/
Dpinctrl_soc.h4 * SPDX-License-Identifier: Apache-2.0
147 #define MIO39 39
148 #define MIO40 40
163 /* MIO pin groups (from Xilinx UG585 v1.13, table 2-4 "MIO-at-a-Glance") */
165 #define MIO_GROUP_ETHERNET1_0_GRP_PINS 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39
180 #define MIO_GROUP_SPI0_2_GRP_PINS 40, 41, 45
195 #define MIO_GROUP_SPI1_2_SS2_PINS 39
202 #define MIO_GROUP_SDIO0_2_GRP_PINS 40, 41, 42, 43, 44, 45
205 #define MIO_GROUP_SDIO1_2_GRP_PINS 34, 35, 36, 37, 38, 39
213 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39
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/Zephyr-latest/dts/arm/atmel/
Ddma_atmel_same70.h3 * SPDX-License-Identifier: Apache-2.0
48 #define DMA_PERID_PWM1_TX 39
49 #define DMA_PERID_TC0_RX 40
Ddma_atmel_samv71.h3 * SPDX-License-Identifier: Apache-2.0
49 #define DMA_PERID_PWM1_TX 39
50 #define DMA_PERID_TC0_RX 40
/Zephyr-latest/samples/subsys/nvs/
Dsample.yaml10 - nrf52dk/nrf52832
15 - "Id: 1, Address: 192.168.1.1"
16 - "Id: 2, Key: ff fe fd fc fb fa f9 f8"
17 - "Id: 3, Reboot_counter: (.*)"
18 - "Id: 4, Data: DATA"
19 - "Id: 5, Longarray: 0 1 2 3 4 5 6 7 8 9 a b c d e f 10 11 12 13 14 15 16 17 18 19 1a 1b \
21 39 3a 3b 3c 3d 3e 3f 40 41 42 43 44 45 46 47 48 49 4a 4b 4c 4d 4e 4f 50 51 52 53 54 55 \
/Zephyr-latest/include/zephyr/dt-bindings/clock/
Dr8a779f0_cpg_mssr.h4 * SPDX-License-Identifier: Apache-2.0
52 #define R8A779F0_CLK_RPCD2 39
53 #define R8A779F0_CLK_MSO 40
Dr8a7795_cpg_mssr.h4 * SPDX-License-Identifier: Apache-2.0
52 #define R8A7795_CLK_CANFD 39 /* CANFD clock */
53 #define R8A7795_CLK_HDMI 40
Desp32s3_clock.h4 * SPDX-License-Identifier: Apache-2.0
87 #define ESP32_SARADC_MODULE 39
88 #define ESP32_MODULE_MAX 40
/Zephyr-latest/include/zephyr/dt-bindings/interrupt-controller/
Desp-esp32c2-intmux.h4 * SPDX-License-Identifier: Apache-2.0
49 #define FROM_CPU_INTR3_SOURCE 39
50 #define ASSIST_DEBUG_INTR_SOURCE 40
54 /* RISC-V supports priority values from 1 (lowest) to 15.
55 * As interrupt controller for Xtensa and RISC-V is shared, this is
Desp-esp32c3-intmux.h4 * SPDX-License-Identifier: Apache-2.0
49 #define SYSTIMER_TARGET2_EDGE_INTR_SOURCE 39
50 #define SPI_MEM_REJECT_CACHE_INTR_SOURCE 40
73 /* RISC-V supports priority values from 1 (lowest) to 15.
74 * As interrupt controller for Xtensa and RISC-V is shared, this is
/Zephyr-latest/soc/ti/lm3s6965/
Dsoc.h2 * Copyright (c) 2013-2015 Wind River Systems, Inc.
4 * SPDX-License-Identifier: Apache-2.0
11 * This header file is used to specify and describe board-level aspects for
63 #define IRQ_RESERVED3 39
64 #define IRQ_RESERVED4 40
/Zephyr-latest/boards/ti/common/
Dboosterpack_connector.dtsi4 * SPDX-License-Identifier: Apache-2.0
9 compatible = "ti,boosterpack-header";
10 #gpio-cells = <2>;
11 gpio-map = <2 0 &gpio0 23 0>,
37 <39 0 &gpio0 6 0>,
38 <40 0 &gpio0 7 0>;
/Zephyr-latest/boards/arm/v2m_musca_s1/
Dv2m_musca_s1-common.dtsi2 * Copyright (c) 2019-2020 Linaro Limited
4 * SPDX-License-Identifier: Apache-2.0
20 compatible = "arm,cmsdk-timer";
28 interrupts = <39 3 40 3 41 3 43 3>;
29 interrupt-names = "rx", "tx", "rxtim", "err";
31 current-speed = <115200>;
38 interrupt-names = "rx", "tx", "rxtim", "err";
40 current-speed = <115200>;
44 compatible = "arm,cmsdk-gpio";
51 gpio-controller;
[all …]
/Zephyr-latest/boards/arm/v2m_musca_b1/
Dv2m_musca_b1-common.dtsi4 * SPDX-License-Identifier: Apache-2.0
20 compatible = "arm,cmsdk-timer";
28 interrupts = <39 3 40 3 41 3 43 3>;
29 interrupt-names = "rx", "tx", "rxtim", "err";
31 current-speed = <115200>;
38 interrupt-names = "rx", "tx", "rxtim", "err";
40 current-speed = <115200>;
44 compatible = "arm,cmsdk-gpio";
51 gpio-controller;
52 #gpio-cells = <2>;
/Zephyr-latest/soc/arm/beetle/
Dsoc_irq.h4 * SPDX-License-Identifier: Apache-2.0
46 #define IRQ_LLCC_RXEVT_VALID 39 /* Cordio */
47 #define IRQ_LLCC_RXDMAH_DONE 40 /* Cordio */
/Zephyr-latest/samples/subsys/fs/zms/
DREADME.rst1 .. zephyr:code-sample:: zms
3 :relevant-api: zms_high_level_api
40 .. zephyr-app-commands::
41 :zephyr-app: samples/subsys/fs/zms
51 .. code-block:: console
53 *** Booting Zephyr OS build v3.7.0-2383-g624f75400242 ***
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