Lines Matching +full:39 +full:- +full:40
4 * SPDX-License-Identifier: Apache-2.0
147 #define MIO39 39
148 #define MIO40 40
163 /* MIO pin groups (from Xilinx UG585 v1.13, table 2-4 "MIO-at-a-Glance") */
165 #define MIO_GROUP_ETHERNET1_0_GRP_PINS 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39
180 #define MIO_GROUP_SPI0_2_GRP_PINS 40, 41, 45
195 #define MIO_GROUP_SPI1_2_SS2_PINS 39
202 #define MIO_GROUP_SDIO0_2_GRP_PINS 40, 41, 42, 43, 44, 45
205 #define MIO_GROUP_SDIO1_2_GRP_PINS 34, 35, 36, 37, 38, 39
213 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39
225 #define MIO_GROUP_CAN0_7_GRP_PINS 38, 39
237 #define MIO_GROUP_CAN1_8_GRP_PINS 40, 41
248 #define MIO_GROUP_UART0_7_GRP_PINS 38, 39
260 #define MIO_GROUP_UART1_8_GRP_PINS 40, 41
271 #define MIO_GROUP_I2C0_7_GRP_PINS 38, 39
282 #define MIO_GROUP_I2C1_7_GRP_PINS 40, 41
291 #define MIO_GROUP_TTC1_2_GRP_PINS 40, 41
294 #define MIO_GROUP_SWDT0_2_GRP_PINS 38, 39
336 #define MIO_GROUP_GPIO0_39_GRP_PINS 39
337 #define MIO_GROUP_GPIO0_40_GRP_PINS 40
351 #define MIO_GROUP_USB0_0_GRP_PINS 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39
352 #define MIO_GROUP_USB1_0_GRP_PINS 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51
360 /* Iterate over each pinctrl-n phandle child */
367 * - Iterate over each pin in group and populate pinctrl_soc_pin_t
369 * - Iterate over each pin in pins and populate pinctrl_soc_pin_t